timer.vhd

这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity timer is port (
			rst				: in std_logic;
			p1khz			: in std_logic;
			sec				: out std_logic_vector(7 downto 0);
			min				: out std_logic_vector(7 downto 0);
			hour			: out std_logic_vector(7 downto 0)
);			
end entity;

architecture timer of timer is

signal t_1s : std_logic;
signal t_1s_cnt : integer range 0 to 500;
constant t_1s_cnt_limit : integer := 499;
--------------------------------------
signal t_60s : std_logic;
signal t_60s_cnt : integer range 0 to 61;
constant t_60s_cnt_limit : integer := 59;
----------------------------------------
signal t_60min : std_logic;
signal t_60min_cnt : integer range 0 to 61;
constant t_60min_cnt_limit : integer := 59;
----------------------------------------
signal t_hour : std_logic;
signal t_hour_cnt : integer range 0 to 101;


begin

sec <= conv_std_logic_vector(t_60s_cnt,8);
min	<= conv_std_logic_vector(t_60min_cnt,8);
hour <= conv_std_logic_vector(t_hour_cnt,8);


gen_SEC : process(p1khz)
begin
	if rising_edge(p1khz) then
		if t_1s_cnt < t_1s_cnt_limit then
			t_1s_cnt <= t_1s_cnt + 1;
		elsif t_1s_cnt = t_1s_cnt_limit then	
			t_1s_cnt <= 0;
			t_1s <= not t_1s;
		end if;
	end if;		
end process;

setup_sec : process(rst,t_1s)
begin
	if rst='0' then
		t_60s_cnt <= 0;
		t_60s <= '0';
	else
		if rising_edge(t_1s) then
			if t_60s_cnt < t_60s_cnt_limit then
				t_60s_cnt <= t_60s_cnt + 1;
				t_60s <= '0';
			elsif t_60s_cnt = t_60s_cnt_limit then	
				t_60s_cnt <= 0;
				t_60s <= '1';
			end if;	
		end if;
	end if;		
end process;

setup_min : process(rst,t_60s)
begin
	if rst='0' then
		t_60min_cnt <= 0;
		t_60min <= '0';
	else
		if rising_edge(t_60s) then
			if t_60min_cnt < t_60min_cnt_limit then
				t_60min_cnt <= t_60min_cnt + 1;
				t_60min <= '0';
			elsif t_60min_cnt = t_60min_cnt_limit then	
				t_60min_cnt <= 0;
				t_60min <= '1';
			end if;	
		end if;
	end if;		
end process;

setup_hour : process(rst,t_60min)
begin
	if rst='0' then
		t_hour_cnt <= 0;
	else
		if rising_edge(t_60min) then
			t_hour_cnt <= t_hour_cnt + 1;
		end if;
	end if;		
end process;



end architecture ;