gen_1mhz.vhd

来自「这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10」· VHDL 代码 · 共 54 行

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;


entity gen_1mhz is port(
			p12mhz				: in std_logic;
			rst					: in std_logic;
			P1MHz				: out std_logic;
			p1khz				: out std_logic
);
end entity;

architecture gen_clk of gen_1mhz is
	  		
signal P1MHz_clk_cnt : integer range 0 to 9;
signal P1MHz_clk : std_logic;
---------------------------------------
signal t_p1khz : std_logic;
signal p1khz_cnt : integer range 0 to 510;

begin

p1mhz <= P1MHz_clk;

process(p12mhz)
begin
	if rising_edge(p12mhz) then	
		if P1MHz_clk_cnt < 5 then
			P1MHz_clk_cnt <= P1MHz_clk_cnt + 1;
		else
			P1MHz_clk <= not P1MHz_clk;
			P1MHz_clk_cnt <= 0;
		end if;
	end if;			
end process; 

p1khz <= t_p1khz;
process(p1mhz_clk)
begin
	if rising_edge(p1mhz_clk) then	
		if p1khz_cnt < 499 then
			p1khz_cnt <= p1khz_cnt + 1;
		else
			t_p1khz <= not t_p1khz;
			p1khz_cnt <= 0;
		end if;
	end if;			
end process; 

end architecture;