📄 read_data.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity read_data is port(
sa : in std_logic_vector(15 downto 0);
ior : in std_logic;
on_read_reg : out std_logic;
reg_data : out std_logic_vector(7 downto 0)
);
end entity;
architecture read_data of read_data is
begin
process()
reg_data
end process;
end architecture;
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