writeled_and_tx.vhd

这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity writeLED_and_tx is port(
			sa				: in std_logic_vector(15 downto 0);
			ad				: in std_logic_vector(7 downto 0);
			iow				: in std_logic;
			rst				: in std_logic;
			set_tx			: out std_logic;
			p1mhz			: in std_logic;
			x_on_tx			: out std_logic
		
);
end entity;			



architecture writeLED_and_tx of writeLED_and_tx is

component wri_reg8 is port(
		iow			: in std_logic;
		rst			: in std_logic;
		cs			: in std_logic;
		data_in		: in std_logic_vector(7 downto 0);
		data_out	: out std_logic_vector(7 downto 0)
		);
end component;

component tx8 is port(
		rst			: in std_logic;
		p1mhz		: in std_logic;
		data_in 	: in std_logic_vector(7 downto 0);
		tx			: out std_logic;
		start_tx	: in std_logic;
		on_tx 		: out std_logic 
);
end component;

signal st : integer range 0 to 30;
constant st_idle 			: integer := 0;
constant st_tx_cm			: integer := 1;
constant st_tx_sd			: integer := 2;
constant st_tx_cm_wait0		: integer := 4;
constant st_tx_cm_wait1		: integer := 5;
constant st_tx_cm_wait2		: integer := 6;
constant st_tx_sd_wait0		: integer := 7;
constant st_tx_sd_wait1		: integer := 8;
constant st_tx_sd_end		: integer := 9;
constant st_tx_sd_end_wait	: integer := 10;

----cs_cm_led(1 downto 0)发射方法：蛇行：01，旋回：10，全亮：00。
--cs_cm_led(3 downto 2)包括"准备"，"投放"，"故障"三个LED
--准备：01，投放：10，故障：11，全亮：00。
--cm(3 7 downto 4):cm_led
signal cs_cm_code_led : std_logic;
signal cm_code_led : std_logic_vector(7 downto 0);

signal cs_sd_led : std_logic;
signal sd_led :  std_logic_vector(7 downto 0);

signal temp_tx : std_logic_vector(7 downto 0);
signal t_start_tx,t_on_tx : std_logic;
signal on_send_com,end_send_com : std_logic;

begin


--写CM指示灯编码
cs_cm_code_led <= '0' when sa = x"c002" else '1';
u_cm_code : wri_reg8 port map(iow,rst,cs_cm_code_led,ad,cm_code_led);

--写SD
cs_sd_led <= '0' when sa = x"c003" else '1';
u_sd_led : wri_reg8 port map(iow,rst,cs_sd_led,ad,sd_led);

x_on_tx <= t_on_tx;

u : tx8 port map(
		rst			=> rst,--: in std_logic;
		p1mhz		=> p1mhz,--: in std_logic;
		data_in 	=> temp_tx,--: in std_logic_vector(7 downto 0);
		tx			=> set_tx,--: out std_logic;
		start_tx	=> t_start_tx,--: in std_logic;
		on_tx 		=> t_on_tx);--out std_logic

process(rst,iow,sa)
begin
	if rst='0' or end_send_com='1' then
		on_send_com <= '0';
	else	
		if rising_edge(iow) then	
			if sa=x"c003" then
				on_send_com <= '1';
			end if;
		end if;
	end if;			
end process;


process(rst,p1mhz,st,t_on_tx,p1mhz,temp_tx)
begin
	if rst='0' then
		st <= st_idle;
		t_start_tx <= '0';
		end_send_com <= '0';
	else
		if rising_edge(p1mhz) then	
			case st is
				when st_idle =>
					end_send_com <= '0';
					if on_send_com='1' then
						st <= st_tx_cm;
						temp_tx <= cm_code_led;
					else
						st <= st_idle;
					end if;
				when st_tx_cm =>
					t_start_tx <= '1';
					st <= st_tx_cm_wait0;
				when st_tx_cm_wait0 =>
					t_start_tx <= '0';	
					st <= st_tx_cm_wait1;
				when st_tx_cm_wait1 =>
					if t_on_tx='0' then
						st <= st_tx_cm_wait1;
					else
						st <= st_tx_cm_wait2;
					end if;
				when st_tx_cm_wait2 =>
					if t_on_tx='1' then
						st <= st_tx_cm_wait2;
					else
						st <= st_tx_sd;
					end if;	
				when st_tx_sd =>
					t_start_tx <= '1';
					temp_tx <= sd_led;
					st <= st_tx_sd_wait0;
				when st_tx_sd_wait0 =>
					t_start_tx <= '0';
					st <= st_tx_sd_wait1;
				when st_tx_sd_wait1 =>	
					if t_on_tx='1' then
						st <= st_tx_sd_wait1;
					else
						st <= st_tx_sd_end;
					end if;		
				when st_tx_sd_end =>
					end_send_com <= '1';
					st <= st_tx_sd_end_wait;
				when st_tx_sd_end_wait =>
					end_send_com <= '0';	
					st <= st_idle;			
				when others =>
					st <= st_idle;
			end case;
		end if;
	end if;							
end process;

end ;