exm_self.vhd

这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试

--这些检测包括：
--1. 在发出交连信号前检测A3输出信号：
--     发出"打开仓门"信号，读"打开仓门"输出返回信号；
--     发出"允许投放"信号，读"允许投放"输出返回信号；
--     发出"战术投放"信号，读"战术投放"输出返回信号；

--启动自检：上电后，在RST上升沿开始，等待CPU在SA=X"C007"写0X55。
--          同时点亮"CPU错"。

--最后，如果测试全部通过，在p1.7-p1.0写0x55。
--如果有出错，则在p1.7-p1.0写0xf0。
library ieee;

use ieee.std_logic_1164.ALL;

ENTITY exm_self is port(
			rst					: in std_logic;
			p1mhz				: in std_logic;
			open_out_drv		: out std_logic;
			allow_out_drv		: out std_logic;
			fight_put_out_drv	: out std_logic;
			rd_rio_a3a			: out std_logic;
			sa					: in std_logic_vector(15 downto 0);
			sd_in				: in std_logic_vector(7 downto 0);
			iow					: in std_logic;
			cpu_err_drv 		: out std_logic;
			ad_err_drv			: out std_logic;
			rio_err_drv			: out std_logic
);
end entity;

architecture exm of exm_self is

signal st : integer range 0 to 63;
constant st_idle					: integer := 0;
constant st_cpu_err_delay			: integer := 1;
constant st_test_ad					: integer := 2;
--constant st_test_ad					: integer := 3;

signal beg_test,end_test : std_logic;
signal delay_time : integer range 0 to 2100;

begin

main : process(rst,p1mhz)
begin
	if rst='0' then
		st <= st_idle;
		end_test <= '0';
		delay_time <= 0;
		open_out_drv	<= '0';
		allow_out_drv	<= '0';
		fight_put_out_drv <= '0';
	else
		if rising_edge(p1mhz) then	
			case st is
				when st_idle =>
					cpu_err_drv <= '0';--点亮"CPU错"
					if sa=x"c007" and sd_in=x"55" and iow='0' then
						st <= st_cpu_err_delay;
					else
						st <= st_idle;
					end if;	
				when st_cpu_err_delay =>
					if delay_time < 2000 then
						st <= st_cpu_err_delay;
						delay_time <= delay_time + 1;
					else	
						st <= st_test_ad;
						delay_time <= 0;
					end if;
				when st_test_ad =>
								
--				when st_test_a3_relay =>
							
--				when st_test_delay =>
--					if delay_time < 10 then
--						delay_time <= delay_time + 1;
--						st <= st_test_delay;
--					else
--						st <= st_test_read_ret_data;	
--					end if;					
--				when st_test_read_ret_data =>
--					if 	
--					end_test <= '1';
--					st <= st_end_test;
--				when st_end_test =>
--					end_test <= '0';
					st <= st_idle;
				when others =>
				 	st <= st_idle;
			end case;
		end if;
	end if;							
end process;

end architecture ;