get_key_from_rx.vhd

这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity get_key_from_rx is port(
			rst				: in std_logic;
			p1mhz			: in std_logic;
			set_rx			: in std_logic;
			can_read_data	: out std_logic;
			sa				: in std_logic_vector(15 downto 0);				
			set_data		: out std_logic_vector(7 downto 0);
			ior				: in std_logic
			
);
end entity;

architecture get_set_rx of get_key_from_rx is

component rx8 is port(
		rst				: in std_logic;
		p1mhz			: in std_logic;
		rx				: in std_logic;
		data_out		: out std_logic_vector(7 downto 0);
		rx_tag			: out std_logic;
		rst_rx			: in std_logic
);
end component;

signal st : integer range 0 to 15;
constant st_idle 			: integer := 0;
constant st_get_rx0			: integer := 1;
constant st_rst_rx0			: integer := 2;
constant st_rst_rx0_wait	: integer := 3;
constant st_get_rx1			: integer := 4;
constant st_rst_rx1			: integer := 5;
constant st_rst_rx1_wait	: integer := 6;
constant st_get_rx_end		: integer := 7;
constant st_wr_set_data0	: integer := 8;
constant st_wr_set_data1	: integer := 9;

signal cm_data : std_logic_vector(7 downto 0);
signal sd_data : std_logic_vector(7 downto 0);
signal t_rx_tag : std_logic;
signal t_rst_rx : std_logic;
signal t_can_read_data,t_read_data  : std_logic;
signal temp_rx : std_logic_vector(7 downto 0);

begin


gen_read_tag : process(rst,sa,ior)
begin
	if rst='0' or (sa=x"c011" and ior='0') then
		t_can_read_data <= '0';
	else
		if rising_edge(t_read_data) then	
			t_can_read_data <= '1';
		end if;
	end if;		
end process;

ux : rx8 port map(
		rst				=> rst,--: in std_logic;
		p1mhz			=> p1mhz,--: in std_logic;
		rx				=> set_rx,--: in std_logic;
		data_out		=> temp_rx,--: out std_logic_vector(7 downto 0);
		rx_tag			=> t_rx_tag,--: out std_logic;
		rst_rx			=> t_rst_rx);--: in std_logic

read_data : process(rst,sa,ior,cm_data,sd_data)
begin
	if rst='0' then
		set_data <= x"00";
	elsif sa=x"c010" and ior='0' then	
		set_data <= cm_data;
	elsif sa=x"c011" and ior='0' then
		set_data <= sd_data;
	else
		set_data <= x"00";
	end if;			
end process;

process(rst,p1mhz,temp_rx,t_rst_rx)
begin
	if rst='0' then
		t_rst_rx <= '1';
		t_read_data <= '0';
		st <= st_idle;
	else
		if rising_edge(p1mhz) then	
			case st is
				when st_idle =>
					t_read_data <= '0';
					t_rst_rx <= '1';
					if t_rx_tag='0' then
						st <= st_idle;
					else
						st <= st_get_rx0;--已经读到第一个字节。
					end if;
				when st_get_rx0	=>
					t_rst_rx <= '0';
					if t_rx_tag='1' then
						st <= st_get_rx0;
					else
						cm_data <= temp_rx;
						st <= st_rst_rx0;
					end if;	
				when st_rst_rx0	=>
					t_rst_rx <= '1';
					st <= st_rst_rx0_wait;
				when st_rst_rx0_wait =>
				--等待第二个字节。
					if t_rx_tag='1' then
						st <= st_rst_rx0_wait;
					else
						st <= st_wr_set_data0;	
						t_rst_rx <= '1';	
					end if;	
				when st_wr_set_data0 =>
					st <= st_get_rx1;
				when st_get_rx1	=>
					if t_rx_tag='0' then
						st <= st_get_rx1;
					else
						st <= st_rst_rx1;	
						sd_data <= temp_rx;
					end if;
				when st_rst_rx1	=>
					t_rst_rx <= '0';
					st <= st_rst_rx1_wait;
				when st_rst_rx1_wait =>
					if t_rx_tag='1' then
						st <= st_rst_rx1_wait;
					else
						st <= st_wr_set_data1;	
						t_rst_rx <= '1';	
					end if;	
				when st_wr_set_data1 =>
					st <= st_get_rx_end;
					t_read_data <= '1';
				when st_get_rx_end =>
					t_read_data <= '0';
					st <= st_idle;
				when others =>
					st <= st_idle;
			end case;
		end if;
	end if;							
end process;

end architecture ;