wri_reg8.vhd

来自「这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10」· VHDL 代码 · 共 32 行

library ieee;

use ieee.std_logic_1164.all;

entity wri_reg8 is port(
		iow			: in std_logic;
		rst			: in std_logic;
		cs			: in std_logic;
		data_in		: in std_logic_vector(7 downto 0);
		data_out	: out std_logic_vector(7 downto 0)
		);
end entity;

architecture  wri_reg8 of wri_reg8	is

begin

process(rst,iow,cs)
begin
	if rst='0' then
		data_out <= x"00";
	else
		if rising_edge(iow) then
			if cs='0' then
				data_out <= data_in;
			end if;
		end if;
	end if;				
end process;

end ;