go_sd_cm.vhd

这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity go_sd_cm is port(
		start_y7b_ad	 		: out std_logic;
		x_cda					: out std_logic_vector(2 downto 0);
		sa						: in std_logic_vector(15 downto 0);
		iow						: in std_logic;
		rst						: in std_logic;
		ad_in					: in std_logic_vector(7 downto 0);
		p1mhz					: in std_logic;
		sd_level				: in std_logic_vector(2 downto 0);
		cm_level				: in std_logic_vector(3 downto 0);
		adc_state				: in std_logic_vector(7 downto 0);
		set_sd_level			: in std_logic_vector(2 downto 0);
		set_cm_level			: in std_logic_vector(3 downto 0);
		y7b_work_state			: out std_logic_vector(7 downto 0)--;
--		y7b_sd_drv				: out std_logic;
--		y7b_cm_drv				: out std_logic
);
end entity;

architecture do of go_sd_cm is

component wri_reg8 is port(
		iow			: in std_logic;
		rst			: in std_logic;
		cs			: in std_logic;
		data_in		: in std_logic_vector(7 downto 0);
		data_out	: out std_logic_vector(7 downto 0)
		);
end component;		
		
signal st : integer range 0 to 15;
constant st_idle 						: integer := 0;
constant st_y7b_go						: integer := 1;
constant st_start_adc					: integer := 2;
constant st_start_adc_wait				: integer := 3;
constant st_get_y7b_position			: integer := 4;
constant st_y7b_work					: integer := 5;
constant st_y7b_error					: integer := 6;
constant st_y7b_work_end				: integer := 7;
constant st_y7b_rotate_motor			: integer := 8;
constant st_y7b_rotate_motor_wait		: integer := 9;
constant st_y7b_work_end_wait			: integer := 10;
constant st_y7b_error_wait				: integer := 11;
---------------------------------
signal cs_y7b_com : std_logic;
signal y7b_com : std_logic_vector(7 downto 0);
-----------------------------------------------
signal t_y7b_go_tag : std_logic;
signal t_y7b_go_tag_end : std_logic;

signal ms_time : integer range 0 to 500;
constant ms_time_limit : integer := 499;
signal t_p1khz : std_logic;
--------------------------------
signal go_time : integer range 0 to 10;
signal go_time_out : integer range 0 to 1200;
signal go_time_over : std_logic;
constant go_time_out_limit : integer := 200;

begin

----------------

cs_y7b_com <= '0' when sa=x"c005" else '1';

u_com : wri_reg8 port map(
		iow			=> iow,--: in std_logic;
		rst			=> rst,--: in std_logic;
		cs			=> cs_y7b_com,--: in std_logic;
		data_in		=> ad_in,--: in std_logic_vector(7 downto 0);
		data_out	=> y7b_com--: out std_logic_vector(7 downto 0)
		);

setup_go_y7b_tag : process(rst,iow,ad_in,sa,t_y7b_go_tag_end)
begin
	if rst='0' or t_y7b_go_tag_end = '1'  then
		t_y7b_go_tag <= '0' ;
	else 
		if rising_edge(iow) then	
			if sa=x"c005" then
				if (ad_in(5)='1' and ad_in(4)='0')
					or (ad_in(5)='0' and ad_in(4)='1') then
				 	t_y7b_go_tag <= '1' ;
				end if;
			end if;
		end if;
	end if;			
end process;	

u_ms : process(p1mhz)
begin
	if rising_edge(p1mhz) then
		if ms_time < ms_time_limit then
			ms_time <= ms_time + 1;
		elsif ms_time = ms_time_limit then	
			t_p1khz <= not t_p1khz;
			ms_time <= 0;
		end if;
	end if;		
end process;

setu_go_time_out : process(rst,t_p1khz,t_y7b_go_tag)
begin
	if rst='0' or t_y7b_go_tag='0' then
		go_time_out <= 0;
		go_time_over <= '0';
	else
		if rising_edge(t_p1khz) then
			if t_y7b_go_tag = '1' then
				if go_time_out < go_time_out_limit then
					go_time_out <= go_time_out + 1;
				elsif go_time_out = go_time_out_limit then
					go_time_over <= '1';	
				end if;	
			end if;
		end if;
	end if;			
end process;

go_y7b_machine : process(rst,st,t_y7b_go_tag,p1mhz)
begin
	if rst='0' then
		st <= st_idle;
		t_y7b_go_tag_end <= '0';
		start_y7b_ad <= '0';
		go_time <= 0;
		y7b_work_state	<= x"00";
--		y7b_sd_drv	<= '0';
--		y7b_cm_drv	<= '0';
	else
		if rising_edge(p1mhz) then
			case st is
				when st_idle =>
					t_y7b_go_tag_end <= '0';
					start_y7b_ad <= '0';
--					y7b_sd_drv	<= '0';
--					y7b_cm_drv	<= '0';
					go_time <= 0;
					if t_y7b_go_tag = '1' then
						st <= st_y7b_go;
						y7b_work_state	<= x"00";
					else
						st <= st_idle;
					end if;
				when st_y7b_go =>
					if y7b_com(5)='1' and y7b_com(4)='0' then --sd通道
						x_cda <= "001";
					elsif y7b_com(5)='0' and y7b_com(4)='1' then--cm通道
						x_cda <= "010";
					end if;	
					st <= st_start_adc;
				when st_start_adc =>
					start_y7b_ad <= '0';
					st <= st_start_adc_wait;
				when st_start_adc_wait =>
					start_y7b_ad <= '1';
					st <= st_get_y7b_position;		
				when st_get_y7b_position =>
					if go_time_over = '0' then
						if adc_state = x"88" then
							st <= st_y7b_work;
						elsif adc_state = x"03" then
							st <= st_y7b_error;
						else
							st <= st_get_y7b_position;
						end if;
					else
						st <= st_y7b_error;		
					end if;
				when st_y7b_work =>
					if (y7b_com(5)='1' and sd_level = set_sd_level) or --sd位置判断
						(y7b_com(4)='1' and cm_level = set_cm_level) then--cm位置判断 
						st <= st_y7b_work_end;
					else
						st <= st_y7b_rotate_motor;	
					end if;	
				when st_y7b_rotate_motor =>
					if y7b_com(5)='1' then
						y7b_sd_drv <= '1';
					elsif y7b_com(4)='1' then
						y7b_cm_drv <= '1';	
					end if;
					st <= st_y7b_rotate_motor_wait;
					go_time <= 0;
				when st_y7b_rotate_motor_wait =>
					if go_time < 5 then
						go_time <= go_time + 1;
						st <= st_y7b_rotate_motor_wait;
					else
						st <= st_start_adc;
					end if;		 	
				when st_y7b_work_end =>
					t_y7b_go_tag_end <= '1';		
					st <= st_y7b_work_end_wait;
				when st_y7b_work_end_wait =>
					t_y7b_go_tag_end <= '0';
					y7b_work_state <= x"aa";
					st <= st_idle;	
				when st_y7b_error =>
					st <= st_y7b_error_wait;
					y7b_work_state <= x"33";	
					t_y7b_go_tag_end <= '1';
				when st_y7b_error_wait =>
					t_y7b_go_tag_end <= '0';	
				 	st <= st_idle;					
				when others =>
					st <= st_idle;
			end case;
		end if;
	end if;							

end process;

end architecture;