time_out.vhd

这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity time_out is port (
		rst						: in std_logic;
		sa						: in std_logic_vector(15 downto 0);
		iow						: in std_logic;
		ad_in					: in std_logic_vector(7 downto 0);
		p1khz					: in std_logic;
		y7b_time_out_tag		: out std_logic_vector(7 downto 0);
		sec1_time_out_tag		: out std_logic_vector(7 downto 0)
		
		
		
);	
end entity;			

architecture time of time_out is

--------------------------------
signal y7b_time_out_cnt : integer range 0 to 2010;
constant y7b_time_out_cnt_limit : integer := 2000;
---------------------------------
signal Y7B_tag,y7b_end_tag : std_logic;
--------------------------------
--------------------------------
signal sec1_time_out_cnt : integer range 0 to 1010;
constant sec1_time_out_cnt_limit : integer := 1000;
---------------------------------
signal sec1_tag,sec1_end_tag : std_logic;


begin


setup_y7b_time_out_tag : process(rst,sa,iow,ad_in,y7b_end_tag)
begin
	if rst='0' or y7b_end_tag = '1' 
		or (sa=x"c005" and iow='0' and ad_in(5 downto 4) = "00") then
		Y7B_tag <= '0';
	else
		if rising_edge(iow) then	  
			if (sa=x"c005" and iow='0' and (ad_in(4)='1' or ad_in(5)='1')) then
				Y7B_tag <= '1';
			end if;
		end if;
	end if;			
end process;

y7b_time_cnt : process(rst,Y7B_tag,p1khz,sa,iow,ad_in)
begin
	if rst='0' or Y7B_tag='0' then
		y7b_time_out_cnt <= 0;
		y7b_end_tag <= '0';
	elsif (sa=x"c005" and iow='0' and ad_in(5 downto 4) = "00") then
		y7b_time_out_tag <= x"00";	
	else
		if rising_edge(p1khz)then
			if Y7B_tag = '1' then
				if y7b_time_out_cnt < y7b_time_out_cnt_limit then
					y7b_time_out_tag <= x"00";
					y7b_time_out_cnt <= y7b_time_out_cnt + 1;
				elsif y7b_time_out_cnt = y7b_time_out_cnt_limit then	
					y7b_end_tag <= '1';
					y7b_time_out_tag <= x"33";
				end if;
			end if;
		end if;
	end if;				
end process;

--------------------------------------------
setup_sec1_time_out_tag : process(rst,sa,iow,ad_in,sec1_end_tag)
begin
	if rst='0' or sec1_end_tag = '1' then
		sec1_tag <= '0';
	else
		if rising_edge(iow) then	  
			if sa=x"c00a" and ad_in = x"80" then
				sec1_tag <= '1';
			end if;
		end if;
	end if;			
end process;

sec1_time_cnt : process(rst,sec1_tag,p1khz,sa,iow,ad_in)
begin
	if rst='0' or sec1_tag='0' then
		sec1_time_out_cnt <= 0;
		sec1_end_tag <= '0';
	elsif (sa=x"c00a" and iow='0' and ad_in = x"80") then
		sec1_time_out_tag <= x"00";	
	else
		if rising_edge(p1khz)then
			if sec1_tag = '1' then
				if sec1_time_out_cnt < sec1_time_out_cnt_limit then
					sec1_time_out_tag <= x"00";
					sec1_time_out_cnt <= sec1_time_out_cnt + 1;
				elsif sec1_time_out_cnt = sec1_time_out_cnt_limit then	
					sec1_end_tag <= '1';
					sec1_time_out_tag <= x"cc";
				end if;
			end if;
		end if;
	end if;				
end process;

end architecture;