cpu.fit.eqn

这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试

U3_clk_cnt[5]_lut_out = T42_cs_buffer[5];
U3_clk_cnt[5] = DFFEA(U3_clk_cnt[5]_lut_out, GLOBAL(D1_P1MHz), !W1L61, , U3L31, , );


--U3_clk_cnt[4] is read_return_pre_set:u_rx_tx|tx16:u_tx|data_clk:u_data_clk|clk_cnt[4] at LC4_B2
--operation mode is normal

U3_clk_cnt[4]_lut_out = T42_cs_buffer[4];
U3_clk_cnt[4] = DFFEA(U3_clk_cnt[4]_lut_out, GLOBAL(D1_P1MHz), !W1L61, , U3L31, , );


--U3_clk_cnt[3] is read_return_pre_set:u_rx_tx|tx16:u_tx|data_clk:u_data_clk|clk_cnt[3] at LC2_B3
--operation mode is normal

U3_clk_cnt[3]_lut_out = T42_cs_buffer[3] & U3L31;
U3_clk_cnt[3] = DFFEA(U3_clk_cnt[3]_lut_out, GLOBAL(D1_P1MHz), !W1L61, , A1L352, , );


--U3_clk_cnt[2] is read_return_pre_set:u_rx_tx|tx16:u_tx|data_clk:u_data_clk|clk_cnt[2] at LC3_B3
--operation mode is normal

U3_clk_cnt[2]_lut_out = T42_cs_buffer[2] & U3L31;
U3_clk_cnt[2] = DFFEA(U3_clk_cnt[2]_lut_out, GLOBAL(D1_P1MHz), !W1L61, , A1L352, , );


--U3_clk_cnt[1] is read_return_pre_set:u_rx_tx|tx16:u_tx|data_clk:u_data_clk|clk_cnt[1] at LC4_B3
--operation mode is normal

U3_clk_cnt[1]_lut_out = T42_cs_buffer[1] & U3L31;
U3_clk_cnt[1] = DFFEA(U3_clk_cnt[1]_lut_out, GLOBAL(D1_P1MHz), !W1L61, , A1L352, , );


--U3L41 is read_return_pre_set:u_rx_tx|tx16:u_tx|data_clk:u_data_clk|LessThan~86 at LC5_B2
--operation mode is normal

U3L41 = U3L51 & !U3L71 # !U3_clk_cnt[6] # !U3_clk_cnt[7];


--U3L31 is read_return_pre_set:u_rx_tx|tx16:u_tx|data_clk:u_data_clk|LessThan~40 at LC2_B2
--operation mode is normal

U3L31 = U3L41 & !U3_clk_cnt[8] & !U3_clk_cnt[9];


--U3L81 is read_return_pre_set:u_rx_tx|tx16:u_tx|data_clk:u_data_clk|t_clk~0 at LC1_B2
--operation mode is normal

U3L81 = !U3L61 & !U3L31 & U3L71 & U3L51;


--V1L62 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[10]~5 at LC6_B28
--operation mode is normal

V1L62 = P5_q[3] & P5_q[1] & V1L21 & !P5_q[0];


--U2L31 is read_return_pre_set:u_rx_tx|rx16:u_rx|data_clk:u_data_clk|gen_clk~0 at LC8_B27
--operation mode is normal

U2L31 = !V1_en_rx # !rst;


--U2_clk_cnt[8] is read_return_pre_set:u_rx_tx|rx16:u_rx|data_clk:u_data_clk|clk_cnt[8] at LC8_F29
--operation mode is normal

U2_clk_cnt[8]_lut_out = T12_cs_buffer[8];
U2_clk_cnt[8] = DFFEA(U2_clk_cnt[8]_lut_out, GLOBAL(D1_P1MHz), !U2L31, , U2L41, , );


--U2_clk_cnt[9] is read_return_pre_set:u_rx_tx|rx16:u_rx|data_clk:u_data_clk|clk_cnt[9] at LC7_F29
--operation mode is normal

U2_clk_cnt[9]_lut_out = R7_unreg_res_node[9];
U2_clk_cnt[9] = DFFEA(U2_clk_cnt[9]_lut_out, GLOBAL(D1_P1MHz), !U2L31, , U2L41, , );


--U2_clk_cnt[7] is read_return_pre_set:u_rx_tx|rx16:u_rx|data_clk:u_data_clk|clk_cnt[7] at LC7_F36
--operation mode is normal

U2_clk_cnt[7]_lut_out = T12_cs_buffer[7] & U2L41;
U2_clk_cnt[7] = DFFEA(U2_clk_cnt[7]_lut_out, GLOBAL(D1_P1MHz), !U2L31, , A1L552, , );


--U2_clk_cnt[6] is read_return_pre_set:u_rx_tx|rx16:u_rx|data_clk:u_data_clk|clk_cnt[6] at LC5_F36
--operation mode is normal

U2_clk_cnt[6]_lut_out = T12_cs_buffer[6] & U2L41;
U2_clk_cnt[6] = DFFEA(U2_clk_cnt[6]_lut_out, GLOBAL(D1_P1MHz), !U2L31, , A1L552, , );


--U2_clk_cnt[5] is read_return_pre_set:u_rx_tx|rx16:u_rx|data_clk:u_data_clk|clk_cnt[5] at LC6_F29
--operation mode is normal

U2_clk_cnt[5]_lut_out = T12_cs_buffer[5];
U2_clk_cnt[5] = DFFEA(U2_clk_cnt[5]_lut_out, GLOBAL(D1_P1MHz), !U2L31, , U2L41, , );


--U2_clk_cnt[4] is read_return_pre_set:u_rx_tx|rx16:u_rx|data_clk:u_data_clk|clk_cnt[4] at LC4_F36
--operation mode is normal

U2_clk_cnt[4]_lut_out = T12_cs_buffer[4];
U2_clk_cnt[4] = DFFEA(U2_clk_cnt[4]_lut_out, GLOBAL(D1_P1MHz), !U2L31, , U2L41, , );


--U2_clk_cnt[3] is read_return_pre_set:u_rx_tx|rx16:u_rx|data_clk:u_data_clk|clk_cnt[3] at LC1_F27
--operation mode is normal

U2_clk_cnt[3]_lut_out = T12_cs_buffer[3] & U2L41;
U2_clk_cnt[3] = DFFEA(U2_clk_cnt[3]_lut_out, GLOBAL(D1_P1MHz), !U2L31, , A1L552, , );


--U2_clk_cnt[2] is read_return_pre_set:u_rx_tx|rx16:u_rx|data_clk:u_data_clk|clk_cnt[2] at LC2_F27
--operation mode is normal

U2_clk_cnt[2]_lut_out = T12_cs_buffer[2] & U2L41;
U2_clk_cnt[2] = DFFEA(U2_clk_cnt[2]_lut_out, GLOBAL(D1_P1MHz), !U2L31, , A1L552, , );


--U2_clk_cnt[1] is read_return_pre_set:u_rx_tx|rx16:u_rx|data_clk:u_data_clk|clk_cnt[1] at LC4_F27
--operation mode is normal

U2_clk_cnt[1]_lut_out = T12_cs_buffer[1] & U2L41;
U2_clk_cnt[1] = DFFEA(U2_clk_cnt[1]_lut_out, GLOBAL(D1_P1MHz), !U2L31, , A1L552, , );


--U2L51 is read_return_pre_set:u_rx_tx|rx16:u_rx|data_clk:u_data_clk|LessThan~86 at LC1_F25
--operation mode is normal

U2L51 = U2L61 & !U2L81 # !U2_clk_cnt[6] # !U2_clk_cnt[7];


--U2L41 is read_return_pre_set:u_rx_tx|rx16:u_rx|data_clk:u_data_clk|LessThan~40 at LC2_F25
--operation mode is normal

U2L41 = U2L51 & !U2_clk_cnt[8] & !U2_clk_cnt[9];


--U2L91 is read_return_pre_set:u_rx_tx|rx16:u_rx|data_clk:u_data_clk|t_clk~0 at LC3_F25
--operation mode is normal

U2L91 = !U2L71 & !U2L41 & U2L81 & U2L61;


--P5L21 is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[4]~18 at LC3_B33
--operation mode is normal

P5L21 = V1_en_rx & P5L11 # !P5_q[4];


--V1_en_rx_end is read_return_pre_set:u_rx_tx|rx16:u_rx|en_rx_end at LC1_F36
--operation mode is normal

V1_en_rx_end_lut_out = VCC;
V1_en_rx_end = DFFEA(V1_en_rx_end_lut_out, !U2_data_clk, !U2L31, , V1L3, , );


--V1L8 is read_return_pre_set:u_rx_tx|rx16:u_rx|stup_en_rx~0 at LC3_F36
--operation mode is normal

V1L8 = V1_en_rx_end # !rst;


--V1L6 is read_return_pre_set:u_rx_tx|rx16:u_rx|reduce_nor~0 at LC6_B33
--operation mode is normal

V1L6 = !P5_q[4] & !P5_q[0] & P5L11;


--G1_t_beg_rst_rx is read_return_pre_set:u_rx_tx|t_beg_rst_rx at LC3_E22
--operation mode is normal

G1_t_beg_rst_rx_lut_out = VCC;
G1_t_beg_rst_rx = DFFEA(G1_t_beg_rst_rx_lut_out, V1_rx_tag, !G1L41, , , , );


--G1L4 is read_return_pre_set:u_rx_tx|process0~0 at LC2_E22
--operation mode is normal

G1L4 = !G1_t_beg_rst_rx # !rst;


--W1L91 is read_return_pre_set:u_rx_tx|tx16:u_tx|reduce_nor~0 at LC2_B36
--operation mode is normal

W1L91 = P6_q[4] & W1L81 & P6_q[0] & P6_q[1];


--N1_adc_state[1] is do_adc:u_ad|sig_adc:u_sig_adc|adc_state[1] at LC8_E26
--operation mode is normal

N1_adc_state[1]_lut_out = N1L641 # N1_adc_state[1] & N1L741;
N1_adc_state[1] = DFFEA(N1_adc_state[1]_lut_out, GLOBAL(p12mhz), rst, , , , );


--N1_adc_state[7] is do_adc:u_ad|sig_adc:u_sig_adc|adc_state[7] at LC5_E26
--operation mode is normal

N1_adc_state[7]_lut_out = N1L821 & N1L841 # N1_adc_state[7] & N1L741 # !N1L821 & N1_adc_state[7] & N1L741;
N1_adc_state[7] = DFFEA(N1_adc_state[7]_lut_out, GLOBAL(p12mhz), rst, , , , );


--B1L941 is do_adc:u_ad|Mux~1962 at LC1_E10
--operation mode is normal

B1L941 = B1_st[0] & B1_st[1] & !N1_adc_state[1] & !N1_adc_state[7];


--P1_q[7] is do_adc:u_ad|lpm_counter:t_cda_rtl_1|alt_counter_f10ke:wysi_counter|q[7] at LC8_E24
--operation mode is clrb_cntr

P1_q[7]_lut_out = (P1_q[7] $ (B1L431 & P1L51)) & P1L71;
P1_q[7] = DFFEA(P1_q[7]_lut_out, GLOBAL(p12mhz), rst, , B1L431, , );


--P1_q[6] is do_adc:u_ad|lpm_counter:t_cda_rtl_1|alt_counter_f10ke:wysi_counter|q[6] at LC7_E24
--operation mode is clrb_cntr

P1_q[6]_lut_out = (P1_q[6] $ (B1L431 & P1L31)) & P1L71;
P1_q[6] = DFFEA(P1_q[6]_lut_out, GLOBAL(p12mhz), rst, , B1L431, , );

--P1L51 is do_adc:u_ad|lpm_counter:t_cda_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT at LC7_E24
--operation mode is clrb_cntr

P1L51 = CARRY(P1_q[6] & P1L31);


--B1L801 is do_adc:u_ad|LessThan~3438 at LC2_E25
--operation mode is normal

B1L801 = !P1_q[7] & !P1_q[6] & !P1_q[1] # !P1_q[2];


--P1_q[5] is do_adc:u_ad|lpm_counter:t_cda_rtl_1|alt_counter_f10ke:wysi_counter|q[5] at LC6_E24
--operation mode is clrb_cntr

P1_q[5]_lut_out = (P1_q[5] $ (B1L431 & P1L11)) & P1L71;
P1_q[5] = DFFEA(P1_q[5]_lut_out, GLOBAL(p12mhz), rst, , B1L431, , );

--P1L31 is do_adc:u_ad|lpm_counter:t_cda_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT at LC6_E24
--operation mode is clrb_cntr

P1L31 = CARRY(P1_q[5] & P1L11);


--P1_q[4] is do_adc:u_ad|lpm_counter:t_cda_rtl_1|alt_counter_f10ke:wysi_counter|q[4] at LC5_E24
--operation mode is clrb_cntr

P1_q[4]_lut_out = (P1_q[4] $ (B1L431 & P1L9)) & P1L71;
P1_q[4] = DFFEA(P1_q[4]_lut_out, GLOBAL(p12mhz), rst, , B1L431, , );

--P1L11 is do_adc:u_ad|lpm_counter:t_cda_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT at LC5_E24
--operation mode is clrb_cntr

P1L11 = CARRY(P1_q[4] & P1L9);


--P1_q[3] is do_adc:u_ad|lpm_counter:t_cda_rtl_1|alt_counter_f10ke:wysi_counter|q[3] at LC4_E24
--operation mode is clrb_cntr

P1_q[3]_lut_out = (P1_q[3] $ (B1L431 & P1L7)) & P1L71;
P1_q[3] = DFFEA(P1_q[3]_lut_out, GLOBAL(p12mhz), rst, , B1L431, , );

--P1L9 is do_adc:u_ad|lpm_counter:t_cda_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT at LC4_E24
--operation mode is clrb_cntr

P1L9 = CARRY(P1_q[3] & P1L7);


--B1L901 is do_adc:u_ad|LessThan~3439 at LC1_E25
--operation mode is normal

B1L901 = B1L801 & !P1_q[5] & !P1_q[4] & !P1_q[3];


--B1L051 is do_adc:u_ad|Mux~1963 at LC2_E9
--operation mode is normal

B1L051 = B1_st[1] & B1L901 # !B1_st[3] # !B1_st[1] & B1_t_can_con_adc # B1_st[3];


--B1L151 is do_adc:u_ad|Mux~1964 at LC2_E10
--operation mode is normal

B1L151 = B1_st[3] & B1L941 # B1L051 & !B1_st[0] # !B1_st[3] & B1L051 & !B1_st[0];


--B1L251 is do_adc:u_ad|Mux~1965 at LC3_E10
--operation mode is normal

B1L251 = !B1_st[0] & !B1_st[1] & B1_st[3] $ N1_adc_state[1];


--B1L161 is do_adc:u_ad|reduce_nor~9 at LC1_E9
--operation mode is normal

B1L161 = N1_adc_state[1] # N1_adc_state[7];


--B1L241 is do_adc:u_ad|Mux~847 at LC3_E9
--operation mode is normal

B1L241 = B1_st[1] & B1L901 # B1_st[2] # !B1_st[1] & B1L161 # !B1_st[2];


--B1L141 is do_adc:u_ad|Mux~846 at LC5_E9
--operation mode is normal

B1L141 = B1_st[2] & B1_st[1] # N1_adc_state[1] $ N1_adc_state[7] # !B1_st[2] & !B1_st[1];


--B1L341 is do_adc:u_ad|Mux~858 at LC6_E9
--operation mode is normal

B1L341 = B1_st[0] & B1_st[3] # !B1_st[0] & B1_st[3] & !B1L241 # !B1_st[3] & !B1L141;


--B1L351 is do_adc:u_ad|Mux~1967 at LC7_E9
--operation mode is normal

B1L351 = B1_st[2] # N1_adc_state[1] # N1_adc_state[7] # !B1_st[1];


--B1L931 is do_adc:u_ad|Mux~840 at LC1_E7
--operation mode is normal

B1L931 = B1_st[0] # B1_st[1] # N1_adc_state[1] $ N1_adc_state[7];


--B1L641 is do_adc:u_ad|Mux~868 at LC4_E9
--operation mode is normal

B1L641 = B1_st[1] & B1_st[0] & B1L161 # !B1_st[0] & !B1L901 # !B1_st[1] & !B1_st[0];


--B1L451 is do_adc:u_ad|Mux~1968 at LC8_E14
--operation mode is normal

B1L451 = B1_st[0] & B1_st[1];


--B1L441 is do_adc:u_ad|Mux~860 at LC4_E7
--operation mode is normal

B1L441 = B1_st[2] & B1_st[3] # !B1_st[2] & B1_st[3] & B1L641 # !B1_st[3] & B1L451;


--B1L041 is do_adc:u_ad|Mux~841 at LC5_E7
--operation mode is normal

B1L041 = !B1_st[0] & !B1_st[1] & N1_adc_state[1] # N1_adc_state[7];


--B1L551 is do_adc:u_ad|Mux~1969 at LC5_E10
--operation mode is normal

B1L551 = !B1_st[1] & B1_st[0] # N1_adc_state[1] $ N1_adc_state[7];


--B1L541 is do_adc:u_ad|Mux~862 at LC6_E10
--operation mode is normal

B1L541 = B1_st[3] & B1_st[2] # !B1_st[3] & B1_st[2] & B1L551 # !B1_st[2] & B1L451;


--B1L651 is do_adc:u_ad|Mux~1970 at LC7_E10
--operation mode is normal

B1L651 = !B1_st[0] & !B1_st[1];


--B1L731 is do_adc:u_ad|Mux~780 at LC6_E7
--operation mode is normal

B1L731 = B1_st[0] & !B1_st[1] & !B1_st[2] & B1_st[3] # !B1_st[0] & B1_st[1] & B1_st[2] & !B1_st[3];


--B1L531 is do_adc:u_ad|Mux~731 at LC8_E7
--operation mode is normal

B1L531 = B1_st[0] & !B1_st[1] & !B1_st[2] & B1_st[3] # !B1_st[0] & !B1_st[3] & B1_st[1] $ !B1_st[2];


--N1_ad_delay_time[6] is do_adc:u_ad|sig_adc:u_sig_adc|ad_delay_time[6] at LC2_D36
--operation mode is normal

N1_ad_delay_time[6]_lut_out = N1_st[3] & N1L151 # !N1_st[3] & N1L301;
N1_ad_delay_time[6] = DFFEA(N1_ad_delay_time[6]_lut_out, GLOBAL(p12mhz), rst, , , , );


--N1_ad_delay_time[7] is do_adc:u_ad|sig_adc:u_sig_adc|ad_delay_time[7] at LC3_D35
--operation mode is normal

N1_ad_delay_time[7]_lut_out = N1_st[3] & N1L651 # !N1_st[3] & N1L101;
N1_ad_delay_time[7] = DFFEA(N1_ad_delay_time[7]_lut_out, GLOBAL(p12mhz), rst, , , , );


--N1L93 is do_adc:u_ad|sig_adc:u_sig_adc|ad_delay_time[5]~585 at LC2_D35
--operation mode is normal

N1L93 = !N1_ad_delay_time[6] & !N1_ad_delay_time[7];


--N1_ad_delay_time[5] is do_adc:u_ad|sig_adc:u_sig_adc|ad_delay_time[5] at LC1_D27
--operation mode is normal

N1_ad_delay_time[5]_lut_out = N1_st[3] & N1L951 # !N1_st[3] & N1L501;
N1_ad_delay_time[5] = DFFEA(N1_ad_delay_time[5]_lut_out, GLOBAL(p12mhz), rst, , , , );


--N1_ad_delay_time[9] is do_adc:u_ad|sig_adc:u_sig_adc|ad_delay_time[9] at LC1_D24
--operation mode is normal

N1_ad_delay_time[9]_lut_out = N1_st[3] & N1L261 # !N1_st[3] & N1L79;