cpu.fit.eqn

这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试

--operation mode is clrb_cntr

P01L7 = CARRY(P01_q[2] & P01L5);


--P01_q[1] is tx8:u_tx8|lpm_counter:data_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[1] at LC2_F2
--operation mode is clrb_cntr

P01_q[1]_lut_out = (P01_q[1] $ (P01L11 & P01L3)) & VCC;
P01_q[1] = DFFEA(P01_q[1]_lut_out, !U4_data_clk, !U4L31, , , , );

--P01L5 is tx8:u_tx8|lpm_counter:data_cnt_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT at LC2_F2
--operation mode is clrb_cntr

P01L5 = CARRY(P01_q[1] & P01L3);


--M7_data_out[7] is tx8:u_tx8|wri_reg8:u_write_data|data_out[7] at LC3_F34
--operation mode is normal

M7_data_out[7]_lut_out = A1L151;
M7_data_out[7] = DFFEA(M7_data_out[7]_lut_out, GLOBAL(iow), rst, , K1L8, , );


--P01_q[0] is tx8:u_tx8|lpm_counter:data_cnt_rtl_2|alt_counter_f10ke:wysi_counter|q[0] at LC1_F2
--operation mode is clrb_cntr

P01_q[0]_lut_out = (P01L11 $ P01_q[0]) & VCC;
P01_q[0] = DFFEA(P01_q[0]_lut_out, !U4_data_clk, !U4L31, , , , );

--P01L3 is tx8:u_tx8|lpm_counter:data_cnt_rtl_2|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT at LC1_F2
--operation mode is clrb_cntr

P01L3 = CARRY(P01_q[0]);


--M7_data_out[0] is tx8:u_tx8|wri_reg8:u_write_data|data_out[0] at LC5_F34
--operation mode is normal

M7_data_out[0]_lut_out = A1L5;
M7_data_out[0] = DFFEA(M7_data_out[0]_lut_out, GLOBAL(iow), rst, , K1L8, , );


--M7_data_out[6] is tx8:u_tx8|wri_reg8:u_write_data|data_out[6] at LC6_F34
--operation mode is normal

M7_data_out[6]_lut_out = A1L531;
M7_data_out[6] = DFFEA(M7_data_out[6]_lut_out, GLOBAL(iow), rst, , K1L8, , );


--K1L3 is tx8:u_tx8|Mux~4 at LC7_F34
--operation mode is normal

K1L3 = P01_q[0] & P01_q[1] # !P01_q[0] & P01_q[1] & M7_data_out[0] # !P01_q[1] & M7_data_out[6];


--M7_data_out[1] is tx8:u_tx8|wri_reg8:u_write_data|data_out[1] at LC8_F34
--operation mode is normal

M7_data_out[1]_lut_out = A1L23;
M7_data_out[1] = DFFEA(M7_data_out[1]_lut_out, GLOBAL(iow), rst, , K1L8, , );


--K1L4 is tx8:u_tx8|Mux~5 at LC4_F34
--operation mode is normal

K1L4 = P01_q[0] & K1L3 & M7_data_out[1] # !K1L3 & M7_data_out[7] # !P01_q[0] & K1L3;


--K1L21 is tx8:u_tx8|tx~174 at LC2_F15
--operation mode is normal

K1L21 = P01_q[3] & P01_q[2] # P01_q[1] # K1L4;


--M7_data_out[4] is tx8:u_tx8|wri_reg8:u_write_data|data_out[4] at LC1_F1
--operation mode is normal

M7_data_out[4]_lut_out = A1L201;
M7_data_out[4] = DFFEA(M7_data_out[4]_lut_out, GLOBAL(iow), rst, , K1L8, , );


--M7_data_out[3] is tx8:u_tx8|wri_reg8:u_write_data|data_out[3] at LC4_F33
--operation mode is normal

M7_data_out[3]_lut_out = A1L97;
M7_data_out[3] = DFFEA(M7_data_out[3]_lut_out, GLOBAL(iow), rst, , K1L8, , );


--M7_data_out[2] is tx8:u_tx8|wri_reg8:u_write_data|data_out[2] at LC2_F1
--operation mode is normal

M7_data_out[2]_lut_out = A1L65;
M7_data_out[2] = DFFEA(M7_data_out[2]_lut_out, GLOBAL(iow), rst, , K1L8, , );


--K1L5 is tx8:u_tx8|Mux~6 at LC3_F15
--operation mode is normal

K1L5 = P01_q[1] & P01_q[0] # !P01_q[1] & P01_q[0] & M7_data_out[3] # !P01_q[0] & M7_data_out[2];


--M7_data_out[5] is tx8:u_tx8|wri_reg8:u_write_data|data_out[5] at LC1_F16
--operation mode is normal

M7_data_out[5]_lut_out = A1L811;
M7_data_out[5] = DFFEA(M7_data_out[5]_lut_out, GLOBAL(iow), rst, , K1L8, , );


--K1L6 is tx8:u_tx8|Mux~7 at LC4_F15
--operation mode is normal

K1L6 = P01_q[1] & K1L5 & M7_data_out[5] # !K1L5 & M7_data_out[4] # !P01_q[1] & K1L5;


--K1_en_tx is tx8:u_tx8|en_tx at LC5_F6
--operation mode is normal

K1_en_tx_lut_out = VCC;
K1_en_tx = DFFEA(K1_en_tx_lut_out, GLOBAL(iow), !K1L7, , K1L8, , );


--U4L31 is tx8:u_tx8|data_clk:u_data_clk|gen_clk~2 at LC4_F6
--operation mode is normal

U4L31 = !K1_en_tx # !rst;


--K1L31 is tx8:u_tx8|tx~175 at LC5_F15
--operation mode is normal

K1L31 = K1L21 # U4L31 # P01_q[2] & K1L6;


--K1L41 is tx8:u_tx8|tx~176 at LC7_F15
--operation mode is normal

K1L41 = P01_q[1] & K1L4 # !P01_q[1] & !P01_q[3] & !P01_q[0];


--K1L51 is tx8:u_tx8|tx~177 at LC6_F15
--operation mode is normal

K1L51 = P01_q[4] # K1L31 # K1L41 & !P01_q[2];


--W1L3 is read_return_pre_set:u_rx_tx|tx16:u_tx|LessThan~76 at LC2_B26
--operation mode is normal

W1L3 = W1L81 & !P6_q[1] # !P6_q[0] # !P6_q[4];


--U3_data_clk is read_return_pre_set:u_rx_tx|tx16:u_tx|data_clk:u_data_clk|data_clk at LC6_B21
--operation mode is normal

U3_data_clk_lut_out = !U3_data_clk;
U3_data_clk = DFFEA(U3_data_clk_lut_out, GLOBAL(D1_P1MHz), !W1L61, , U3L81, , );


--V1_t_data[10] is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[10] at LC5_B28
--operation mode is normal

V1_t_data[10]_lut_out = set_rx;
V1_t_data[10] = DFFEA(V1_t_data[10]_lut_out, U2_data_clk, rst, , V1L62, , );


--E1L3 is write_reg:u_read_write|process2~0 at LC1_B28
--operation mode is normal

E1L3 = V1_t_data[10] # !rst;


--K1L01 is tx8:u_tx8|reduce_nor~23 at LC1_B24
--operation mode is normal

K1L01 = M4_data_out[3] & A1L642 & !M4_data_out[4] & !M4_data_out[5];


--E1L9 is write_reg:u_read_write|reduce_nor~5 at LC2_B23
--operation mode is normal

E1L9 = !M4_data_out[1] & !M4_data_out[0] & M4_data_out[2] & K1L01;


--C1L03 is generate_int:u_int|reduce_nor~78 at LC4_B35
--operation mode is normal

C1L03 = A1L642 & !M4_data_out[4] & !M4_data_out[3] & !M4_data_out[5];


--E1L8 is write_reg:u_read_write|reduce_nor~4 at LC8_B6
--operation mode is normal

E1L8 = !M4_data_out[2] & M4_data_out[0] & M4_data_out[1] & C1L03;


--U2_data_clk is read_return_pre_set:u_rx_tx|rx16:u_rx|data_clk:u_data_clk|data_clk at LC6_F25
--operation mode is normal

U2_data_clk_lut_out = !U2_data_clk;
U2_data_clk = DFFEA(U2_data_clk_lut_out, GLOBAL(D1_P1MHz), !U2L31, , U2L91, , );


--P5_q[0] is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|q[0] at LC4_B32
--operation mode is clrb_cntr

P5_q[0]_lut_out = (P5L21 $ P5_q[0]) & VCC;
P5_q[0] = DFFEA(P5_q[0]_lut_out, !U2_data_clk, !U2L31, , , , );

--P5L3 is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT at LC4_B32
--operation mode is clrb_cntr

P5L3 = CARRY(P5_q[0]);


--P5_q[3] is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|q[3] at LC7_B32
--operation mode is clrb_cntr

P5_q[3]_lut_out = (P5_q[3] $ (P5L21 & P5L7)) & VCC;
P5_q[3] = DFFEA(P5_q[3]_lut_out, !U2_data_clk, !U2L31, , , , );

--P5L9 is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT at LC7_B32
--operation mode is clrb_cntr

P5L9 = CARRY(P5_q[3] & P5L7);


--V1_en_rx is read_return_pre_set:u_rx_tx|rx16:u_rx|en_rx at LC5_B33
--operation mode is normal

V1_en_rx_lut_out = VCC;
V1_en_rx = DFFEA(V1_en_rx_lut_out, !set_rx, !V1L8, , V1L6, , );


--P5_q[2] is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|q[2] at LC6_B32
--operation mode is clrb_cntr

P5_q[2]_lut_out = (P5_q[2] $ (P5L21 & P5L5)) & VCC;
P5_q[2] = DFFEA(P5_q[2]_lut_out, !U2_data_clk, !U2L31, , , , );

--P5L7 is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT at LC6_B32
--operation mode is clrb_cntr

P5L7 = CARRY(P5_q[2] & P5L5);


--P5_q[4] is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|q[4] at LC8_B32
--operation mode is clrb_cntr

P5_q[4]_lut_out = (P5_q[4] $ (P5L21 & P5L9)) & VCC;
P5_q[4] = DFFEA(P5_q[4]_lut_out, !U2_data_clk, !U2L31, , , , );


--V1L21 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[0]~255 at LC1_B32
--operation mode is normal

V1L21 = V1_en_rx & !P5_q[2] & !P5_q[4];


--P5_q[1] is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|q[1] at LC5_B32
--operation mode is clrb_cntr

P5_q[1]_lut_out = (P5_q[1] $ (P5L21 & P5L3)) & VCC;
P5_q[1] = DFFEA(P5_q[1]_lut_out, !U2_data_clk, !U2L31, , , , );

--P5L5 is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT at LC5_B32
--operation mode is clrb_cntr

P5L5 = CARRY(P5_q[1] & P5L3);


--V1L42 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[9]~6 at LC3_B30
--operation mode is normal

V1L42 = P5_q[0] & P5_q[3] & V1L21 & !P5_q[1];


--E1L11 is write_reg:u_read_write|reduce_nor~7 at LC3_B23
--operation mode is normal

E1L11 = !M4_data_out[0] & K1L01 & M4_data_out[2] & M4_data_out[1];


--E1L7 is write_reg:u_read_write|reduce_nor~3 at LC1_B6
--operation mode is normal

E1L7 = !M4_data_out[0] & !M4_data_out[2] & C1L03 & M4_data_out[1];


--V1L92 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[13]~256 at LC7_B33
--operation mode is normal

V1L92 = P5_q[2] & V1_en_rx & !P5_q[4];


--V1L02 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[4]~8 at LC1_B34
--operation mode is normal

V1L02 = V1L92 & !P5_q[0] & !P5_q[1] & !P5_q[3];


--V1L81 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[3]~9 at LC4_B30
--operation mode is normal

V1L81 = P5_q[0] & V1L21 & P5_q[1] & !P5_q[3];


--P5L11 is read_return_pre_set:u_rx_tx|rx16:u_rx|lpm_counter:data_cnt_rtl_3|alt_counter_f10ke:wysi_counter|counter_cell[4]~17 at LC2_B33
--operation mode is normal

P5L11 = !P5_q[2] & !P5_q[1] & !P5_q[3];


--V1L53 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[16]~1 at LC1_B33
--operation mode is normal

V1L53 = P5_q[4] & V1_en_rx & P5L11 & !P5_q[0];


--V1L41 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[1]~11 at LC5_B30
--operation mode is normal

V1L41 = P5_q[0] & V1L21 & !P5_q[1] & !P5_q[3];


--V1L33 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[15]~2 at LC2_B34
--operation mode is normal

V1L33 = P5_q[0] & P5_q[1] & P5_q[3] & V1L92;


--V1L61 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[2]~10 at LC3_B32
--operation mode is normal

V1L61 = P5_q[1] & V1L21 & !P5_q[3] & !P5_q[0];


--V1L82 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[13]~4 at LC4_B34
--operation mode is normal

V1L82 = P5_q[3] & V1L92 & P5_q[0] & !P5_q[1];


--E1L01 is write_reg:u_read_write|reduce_nor~6 at LC5_B23
--operation mode is normal

E1L01 = !M4_data_out[1] & M4_data_out[2] & M4_data_out[0] & K1L01;


--V1L13 is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[14]~3 at LC5_B34
--operation mode is normal

V1L13 = P5_q[1] & P5_q[3] & V1L92 & !P5_q[0];


--G1_t_start_tx is read_return_pre_set:u_rx_tx|t_start_tx at LC7_E22
--operation mode is normal

G1_t_start_tx_lut_out = G1L42 & G1_t_start_tx # !G1L31;
G1_t_start_tx = DFFEA(G1_t_start_tx_lut_out, GLOBAL(D1_P1MHz), !G1L4, , G1L52, , );


--W1_end_tx is read_return_pre_set:u_rx_tx|tx16:u_tx|end_tx at LC7_B21
--operation mode is normal

W1_end_tx_lut_out = VCC;
W1_end_tx = DFFEA(W1_end_tx_lut_out, !U3_data_clk, !W1L61, , W1L91, , );


--W1L51 is read_return_pre_set:u_rx_tx|tx16:u_tx|process0~0 at LC3_B4
--operation mode is normal

W1L51 = W1_end_tx # !rst;


--E1L6 is write_reg:u_read_write|reduce_nor~2 at LC4_C33
--operation mode is normal

E1L6 = !M4_data_out[1] & !M4_data_out[0] & M4_data_out[2] & C1L03;


--M3_data_out[2] is write_reg:u_read_write|wri_reg8:u_a3_reg|data_out[2] at LC6_A32
--operation mode is normal

M3_data_out[2]_lut_out = A1L65;
M3_data_out[2] = DFFEA(M3_data_out[2]_lut_out, GLOBAL(iow), rst, , E1L6, , );


--M3_data_out[1] is write_reg:u_read_write|wri_reg8:u_a3_reg|data_out[1] at LC3_C1
--operation mode is normal

M3_data_out[1]_lut_out = A1L23;
M3_data_out[1] = DFFEA(M3_data_out[1]_lut_out, GLOBAL(iow), rst, , E1L6, , );


--B1_st[0] is do_adc:u_ad|st[0] at LC8_E10
--operation mode is normal

B1_st[0]_lut_out = B1_st[2] & B1L251 & !N1_adc_state[7] # !B1_st[2] & B1L151;
B1_st[0] = DFFEA(B1_st[0]_lut_out, GLOBAL(p12mhz), rst, , , , );


--B1_st[1] is do_adc:u_ad|st[1] at LC8_E9
--operation mode is normal

B1_st[1]_lut_out = B1_st[0] & B1L341 & !B1L351 # !B1L341 & !B1_st[1] # !B1_st[0] & B1L341;
B1_st[1] = DFFEA(B1_st[1]_lut_out, GLOBAL(p12mhz), rst, , , , );


--B1_st[2] is do_adc:u_ad|st[2] at LC7_E7
--operation mode is normal

B1_st[2]_lut_out = B1_st[2] & B1L441 & B1L041 # !B1L441 & !B1L931 # !B1_st[2] & B1L441;
B1_st[2] = DFFEA(B1_st[2]_lut_out, GLOBAL(p12mhz), rst, , , , );