cpu.fit.eqn

这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试

--P6_q[4] is read_return_pre_set:u_rx_tx|tx16:u_tx|lpm_counter:data_cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[4] at LC5_B21
--operation mode is clrb_cntr

P6_q[4]_lut_out = (P6_q[4] $ (W1L3 & P6L9)) & VCC;
P6_q[4] = DFFEA(P6_q[4]_lut_out, !U3_data_clk, !W1L61, , W1L3, , );


--P6_q[1] is read_return_pre_set:u_rx_tx|tx16:u_tx|lpm_counter:data_cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[1] at LC2_B21
--operation mode is clrb_cntr

P6_q[1]_lut_out = (P6_q[1] $ (W1L3 & P6L3)) & VCC;
P6_q[1] = DFFEA(P6_q[1]_lut_out, !U3_data_clk, !W1L61, , W1L3, , );

--P6L5 is read_return_pre_set:u_rx_tx|tx16:u_tx|lpm_counter:data_cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT at LC2_B21
--operation mode is clrb_cntr

P6L5 = CARRY(P6_q[1] & P6L3);


--P6_q[0] is read_return_pre_set:u_rx_tx|tx16:u_tx|lpm_counter:data_cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] at LC1_B21
--operation mode is clrb_cntr

P6_q[0]_lut_out = (W1L3 $ P6_q[0]) & VCC;
P6_q[0] = DFFEA(P6_q[0]_lut_out, !U3_data_clk, !W1L61, , W1L3, , );

--P6L3 is read_return_pre_set:u_rx_tx|tx16:u_tx|lpm_counter:data_cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT at LC1_B21
--operation mode is clrb_cntr

P6L3 = CARRY(P6_q[0]);


--P6_q[3] is read_return_pre_set:u_rx_tx|tx16:u_tx|lpm_counter:data_cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[3] at LC4_B21
--operation mode is clrb_cntr

P6_q[3]_lut_out = (P6_q[3] $ (W1L3 & P6L7)) & VCC;
P6_q[3] = DFFEA(P6_q[3]_lut_out, !U3_data_clk, !W1L61, , W1L3, , );

--P6L9 is read_return_pre_set:u_rx_tx|tx16:u_tx|lpm_counter:data_cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT at LC4_B21
--operation mode is clrb_cntr

P6L9 = CARRY(P6_q[3] & P6L7);


--P6_q[2] is read_return_pre_set:u_rx_tx|tx16:u_tx|lpm_counter:data_cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[2] at LC3_B21
--operation mode is clrb_cntr

P6_q[2]_lut_out = (P6_q[2] $ (W1L3 & P6L5)) & VCC;
P6_q[2] = DFFEA(P6_q[2]_lut_out, !U3_data_clk, !W1L61, , W1L3, , );

--P6L7 is read_return_pre_set:u_rx_tx|tx16:u_tx|lpm_counter:data_cnt_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT at LC3_B21
--operation mode is clrb_cntr

P6L7 = CARRY(P6_q[2] & P6L5);


--W1L81 is read_return_pre_set:u_rx_tx|tx16:u_tx|process2~29 at LC2_B20
--operation mode is normal

W1L81 = !P6_q[3] & !P6_q[2];


--W1L02 is read_return_pre_set:u_rx_tx|tx16:u_tx|t_tx~64 at LC3_B36
--operation mode is normal

W1L02 = P6_q[4] & P6_q[1] # !W1L81 # !P6_q[4] & !P6_q[1] & !P6_q[0] & W1L81;


--E1_flash_mode_led is write_reg:u_read_write|flash_mode_led at LC4_B23
--operation mode is normal

E1_flash_mode_led_lut_out = A1L5;
E1_flash_mode_led = DFFEA(E1_flash_mode_led_lut_out, GLOBAL(iow), !E1L3, , E1L9, , );


--E1_t_err_sd_code[7] is write_reg:u_read_write|t_err_sd_code[7] at LC1_B20
--operation mode is normal

E1_t_err_sd_code[7]_lut_out = A1L151;
E1_t_err_sd_code[7] = DFFEA(E1_t_err_sd_code[7]_lut_out, GLOBAL(iow), rst, , E1L8, , );


--V1_t_data[9] is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[9] at LC2_B30
--operation mode is normal

V1_t_data[9]_lut_out = set_rx;
V1_t_data[9] = DFFEA(V1_t_data[9]_lut_out, U2_data_clk, rst, , V1L42, , );


--E1_XT is write_reg:u_read_write|XT at LC6_B23
--operation mode is normal

E1_XT_lut_out = A1L5;
E1_XT = DFFEA(E1_XT_lut_out, GLOBAL(iow), rst, , E1L11, , );


--W1L21 is read_return_pre_set:u_rx_tx|tx16:u_tx|Mux~201 at LC3_B20
--operation mode is normal

W1L21 = E1_XT & E1_t_err_sd_code[7] # !E1_XT & V1_t_data[9];


--E1_t_err_cm_code[0] is write_reg:u_read_write|t_err_cm_code[0] at LC4_B20
--operation mode is normal

E1_t_err_cm_code[0]_lut_out = A1L5;
E1_t_err_cm_code[0] = DFFEA(E1_t_err_cm_code[0]_lut_out, GLOBAL(iow), rst, , E1L7, , );


--W1L31 is read_return_pre_set:u_rx_tx|tx16:u_tx|Mux~202 at LC5_B20
--operation mode is normal

W1L31 = P6_q[1] & W1L21 # !P6_q[1] & E1_t_err_cm_code[0];


--W1L41 is read_return_pre_set:u_rx_tx|tx16:u_tx|Mux~203 at LC6_B20
--operation mode is normal

W1L41 = P6_q[0] & E1_flash_mode_led & P6_q[1] # !P6_q[0] & W1L31;


--E1_t_err_cm_code[1] is write_reg:u_read_write|t_err_cm_code[1] at LC4_B36
--operation mode is normal

E1_t_err_cm_code[1]_lut_out = A1L23;
E1_t_err_cm_code[1] = DFFEA(E1_t_err_cm_code[1]_lut_out, GLOBAL(iow), rst, , E1L7, , );


--E1_t_err_sd_code[3] is write_reg:u_read_write|t_err_sd_code[3] at LC4_B29
--operation mode is normal

E1_t_err_sd_code[3]_lut_out = A1L97;
E1_t_err_sd_code[3] = DFFEA(E1_t_err_sd_code[3]_lut_out, GLOBAL(iow), rst, , E1L8, , );


--V1_t_data[4] is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[4] at LC8_B34
--operation mode is normal

V1_t_data[4]_lut_out = set_rx;
V1_t_data[4] = DFFEA(V1_t_data[4]_lut_out, U2_data_clk, rst, , V1L02, , );


--E1_t_err_cm_code[3] is write_reg:u_read_write|t_err_cm_code[3] at LC1_B19
--operation mode is normal

E1_t_err_cm_code[3]_lut_out = !A1L97;
E1_t_err_cm_code[3] = DFFEA(E1_t_err_cm_code[3]_lut_out, GLOBAL(iow), rst, , E1L7, , );


--G1L92 is read_return_pre_set:u_rx_tx|t_tx_temp[3]~287 at LC5_B29
--operation mode is normal

G1L92 = E1_t_err_cm_code[3] & E1_XT & E1_t_err_sd_code[3] # !E1_XT & V1_t_data[4] # !E1_t_err_cm_code[3] & E1_t_err_sd_code[3];


--V1_t_data[3] is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[3] at LC6_B30
--operation mode is normal

V1_t_data[3]_lut_out = set_rx;
V1_t_data[3] = DFFEA(V1_t_data[3]_lut_out, U2_data_clk, rst, , V1L81, , );


--E1_t_err_sd_code[2] is write_reg:u_read_write|t_err_sd_code[2] at LC6_B29
--operation mode is normal

E1_t_err_sd_code[2]_lut_out = !A1L65;
E1_t_err_sd_code[2] = DFFEA(E1_t_err_sd_code[2]_lut_out, GLOBAL(iow), rst, , E1L8, , );


--G1L82 is read_return_pre_set:u_rx_tx|t_tx_temp[2]~288 at LC7_B29
--operation mode is normal

G1L82 = E1_t_err_cm_code[3] & E1_XT & !E1_t_err_sd_code[2] # !E1_XT & V1_t_data[3] # !E1_t_err_cm_code[3] & !E1_t_err_sd_code[2];


--W1L8 is read_return_pre_set:u_rx_tx|tx16:u_tx|Mux~16 at LC3_B29
--operation mode is normal

W1L8 = P6_q[1] & P6_q[0] # !P6_q[1] & P6_q[0] & G1L92 # !P6_q[0] & G1L82;


--E1_t_err_cm_code[2] is write_reg:u_read_write|t_err_cm_code[2] at LC5_B36
--operation mode is normal

E1_t_err_cm_code[2]_lut_out = A1L65;
E1_t_err_cm_code[2] = DFFEA(E1_t_err_cm_code[2]_lut_out, GLOBAL(iow), rst, , E1L7, , );


--W1L9 is read_return_pre_set:u_rx_tx|tx16:u_tx|Mux~17 at LC1_B36
--operation mode is normal

W1L9 = P6_q[1] & W1L8 & E1_t_err_cm_code[2] # !W1L8 & E1_t_err_cm_code[1] # !P6_q[1] & W1L8;


--E1_t_err_cm_code[7] is write_reg:u_read_write|t_err_cm_code[7] at LC3_B28
--operation mode is normal

E1_t_err_cm_code[7]_lut_out = A1L151;
E1_t_err_cm_code[7] = DFFEA(E1_t_err_cm_code[7]_lut_out, GLOBAL(iow), rst, , E1L7, , );


--V1_t_data[16] is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[16] at LC4_B28
--operation mode is normal

V1_t_data[16]_lut_out = set_rx;
V1_t_data[16] = DFFEA(V1_t_data[16]_lut_out, U2_data_clk, rst, , V1L53, , );


--G1L33 is read_return_pre_set:u_rx_tx|t_tx_temp[15]~289 at LC2_B28
--operation mode is normal

G1L33 = E1_t_err_cm_code[3] & E1_XT & E1_t_err_cm_code[7] # !E1_XT & V1_t_data[16] # !E1_t_err_cm_code[3] & E1_t_err_cm_code[7];


--E1_t_err_sd_code[0] is write_reg:u_read_write|t_err_sd_code[0] at LC2_B29
--operation mode is normal

E1_t_err_sd_code[0]_lut_out = A1L5;
E1_t_err_sd_code[0] = DFFEA(E1_t_err_sd_code[0]_lut_out, GLOBAL(iow), rst, , E1L8, , );


--V1_t_data[1] is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[1] at LC8_B30
--operation mode is normal

V1_t_data[1]_lut_out = set_rx;
V1_t_data[1] = DFFEA(V1_t_data[1]_lut_out, U2_data_clk, rst, , V1L41, , );


--G1L62 is read_return_pre_set:u_rx_tx|t_tx_temp[0]~290 at LC1_B31
--operation mode is normal

G1L62 = E1_t_err_cm_code[3] & E1_XT & E1_t_err_sd_code[0] # !E1_XT & V1_t_data[1] # !E1_t_err_cm_code[3] & E1_t_err_sd_code[0];


--E1_t_err_cm_code[6] is write_reg:u_read_write|t_err_cm_code[6] at LC5_B19
--operation mode is normal

E1_t_err_cm_code[6]_lut_out = A1L531;
E1_t_err_cm_code[6] = DFFEA(E1_t_err_cm_code[6]_lut_out, GLOBAL(iow), rst, , E1L7, , );


--V1_t_data[15] is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[15] at LC7_B34
--operation mode is normal

V1_t_data[15]_lut_out = set_rx;
V1_t_data[15] = DFFEA(V1_t_data[15]_lut_out, U2_data_clk, rst, , V1L33, , );


--G1L23 is read_return_pre_set:u_rx_tx|t_tx_temp[14]~291 at LC3_B31
--operation mode is normal

G1L23 = E1_t_err_cm_code[3] & E1_XT & E1_t_err_cm_code[6] # !E1_XT & V1_t_data[15] # !E1_t_err_cm_code[3] & E1_t_err_cm_code[6];


--W1L6 is read_return_pre_set:u_rx_tx|tx16:u_tx|Mux~14 at LC4_B31
--operation mode is normal

W1L6 = P6_q[0] & P6_q[1] # !P6_q[0] & P6_q[1] & G1L62 # !P6_q[1] & G1L23;


--E1_t_err_sd_code[1] is write_reg:u_read_write|t_err_sd_code[1] at LC8_B29
--operation mode is normal

E1_t_err_sd_code[1]_lut_out = A1L23;
E1_t_err_sd_code[1] = DFFEA(E1_t_err_sd_code[1]_lut_out, GLOBAL(iow), rst, , E1L8, , );


--V1_t_data[2] is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[2] at LC2_B32
--operation mode is normal

V1_t_data[2]_lut_out = set_rx;
V1_t_data[2] = DFFEA(V1_t_data[2]_lut_out, U2_data_clk, rst, , V1L61, , );


--G1L72 is read_return_pre_set:u_rx_tx|t_tx_temp[1]~292 at LC1_B29
--operation mode is normal

G1L72 = E1_t_err_cm_code[3] & E1_XT & E1_t_err_sd_code[1] # !E1_XT & V1_t_data[2] # !E1_t_err_cm_code[3] & E1_t_err_sd_code[1];


--W1L7 is read_return_pre_set:u_rx_tx|tx16:u_tx|Mux~15 at LC2_B31
--operation mode is normal

W1L7 = P6_q[0] & W1L6 & G1L72 # !W1L6 & G1L33 # !P6_q[0] & W1L6;


--W1L4 is read_return_pre_set:u_rx_tx|tx16:u_tx|Mux~12 at LC7_B20
--operation mode is normal

W1L4 = P6_q[3] & P6_q[2] # !P6_q[3] & P6_q[2] & W1L9 # !P6_q[2] & W1L7;


--V1_t_data[13] is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[13] at LC6_B34
--operation mode is normal

V1_t_data[13]_lut_out = set_rx;
V1_t_data[13] = DFFEA(V1_t_data[13]_lut_out, U2_data_clk, rst, , V1L82, , );


--E1_t_err_cm_code[4] is write_reg:u_read_write|t_err_cm_code[4] at LC7_B19
--operation mode is normal

E1_t_err_cm_code[4]_lut_out = !A1L201;
E1_t_err_cm_code[4] = DFFEA(E1_t_err_cm_code[4]_lut_out, GLOBAL(iow), rst, , E1L7, , );


--G1L03 is read_return_pre_set:u_rx_tx|t_tx_temp[12]~293 at LC1_B25
--operation mode is normal

G1L03 = E1_t_err_cm_code[3] & E1_XT & !E1_t_err_cm_code[4] # !E1_XT & V1_t_data[13] # !E1_t_err_cm_code[3] & !E1_t_err_cm_code[4];


--E1_flash_ready_led is write_reg:u_read_write|flash_ready_led at LC1_B23
--operation mode is normal

E1_flash_ready_led_lut_out = A1L5;
E1_flash_ready_led = DFFEA(E1_flash_ready_led_lut_out, GLOBAL(iow), rst, , E1L01, , );


--W1L01 is read_return_pre_set:u_rx_tx|tx16:u_tx|Mux~18 at LC2_B25
--operation mode is normal

W1L01 = P6_q[0] & P6_q[1] # !P6_q[0] & P6_q[1] & G1L03 # !P6_q[1] & E1_flash_ready_led;


--E1_t_err_cm_code[5] is write_reg:u_read_write|t_err_cm_code[5] at LC4_B19
--operation mode is normal

E1_t_err_cm_code[5]_lut_out = A1L811;
E1_t_err_cm_code[5] = DFFEA(E1_t_err_cm_code[5]_lut_out, GLOBAL(iow), rst, , E1L7, , );


--V1_t_data[14] is read_return_pre_set:u_rx_tx|rx16:u_rx|t_data[14] at LC3_B34
--operation mode is normal

V1_t_data[14]_lut_out = set_rx;
V1_t_data[14] = DFFEA(V1_t_data[14]_lut_out, U2_data_clk, rst, , V1L13, , );


--G1L13 is read_return_pre_set:u_rx_tx|t_tx_temp[13]~294 at LC3_B25
--operation mode is normal

G1L13 = E1_t_err_cm_code[3] & E1_XT & E1_t_err_cm_code[5] # !E1_XT & V1_t_data[14] # !E1_t_err_cm_code[3] & E1_t_err_cm_code[5];


--W1L11 is read_return_pre_set:u_rx_tx|tx16:u_tx|Mux~19 at LC8_B25
--operation mode is normal

W1L11 = P6_q[0] & W1L01 & G1L13 # !W1L01 & !E1_t_err_cm_code[3] # !P6_q[0] & W1L01;


--W1L5 is read_return_pre_set:u_rx_tx|tx16:u_tx|Mux~13 at LC8_B20
--operation mode is normal

W1L5 = P6_q[3] & W1L4 & W1L11 # !W1L4 & W1L41 # !P6_q[3] & W1L4;


--W1L71 is read_return_pre_set:u_rx_tx|tx16:u_tx|process2~0 at LC6_B36
--operation mode is normal

W1L71 = P6_q[0] & W1L81 & !P6_q[4] & !P6_q[1];


--W1_en_tx is read_return_pre_set:u_rx_tx|tx16:u_tx|en_tx at LC1_B4
--operation mode is normal

W1_en_tx_lut_out = VCC;
W1_en_tx = DFFEA(W1_en_tx_lut_out, G1_t_start_tx, !W1L51, , , , );


--W1L61 is read_return_pre_set:u_rx_tx|tx16:u_tx|process1~2 at LC8_B4
--operation mode is normal

W1L61 = !W1_en_tx # !rst;


--W1L12 is read_return_pre_set:u_rx_tx|tx16:u_tx|tx~0 at LC7_B36
--operation mode is normal

W1L12 = W1L02 # W1L61 # W1L5 & !W1L71;


--A1L342 is reduce_nor~22 at LC1_B14
--operation mode is normal

A1L342 = sa_h[14] # !sa_h[15];


--M4_data_out[7] is write_reg:u_read_write|wri_reg8:u_adr|data_out[7] at LC2_C31
--operation mode is normal

M4_data_out[7]_lut_out = A1L151;
M4_data_out[7] = DFFEA(M4_data_out[7]_lut_out, !ale, rst, , , , );


--M4_data_out[6] is write_reg:u_read_write|wri_reg8:u_adr|data_out[6] at LC1_F34
--operation mode is normal

M4_data_out[6]_lut_out = A1L531;
M4_data_out[6] = DFFEA(M4_data_out[6]_lut_out, !ale, rst, , , , );


--M4_data_out[5] is write_reg:u_read_write|wri_reg8:u_adr|data_out[5] at LC2_F34
--operation mode is normal

M4_data_out[5]_lut_out = A1L811;
M4_data_out[5] = DFFEA(M4_data_out[5]_lut_out, !ale, rst, , , , );


--M4_data_out[4] is write_reg:u_read_write|wri_reg8:u_adr|data_out[4] at LC7_B35
--operation mode is normal

M4_data_out[4]_lut_out = A1L201;
M4_data_out[4] = DFFEA(M4_data_out[4]_lut_out, !ale, rst, , , , );