testarm.v

arm10_verilog.rar是基于arm10的verilog代码

module test_arm();

reg GCLK;
reg nRESET;
reg BIGEND;
reg [1:0] CHSD, CHSE;
wire LATECANCEL, PASS;
wire [4:0] InM;

arm10 arm10(.nRESET(nRESET), .GCLK(GCLK), .BIGEND(BIGEND),
	  .CHSD(CHSD), .CHSE(CHSE), .LATECANCEL(LATECANCEL),
	     .PASS(PASS), .InM(InM));

initial
begin
	nRESET=1'b1;
	BIGEND=1'b0;
	GCLK=1'b0;
	CHSE = 2'b10;
	CHSD = 2'b10;
	$readmemh("testarm.vhx", arm10.mem);
	#10 nRESET=1'b1;
end

always #50 GCLK = ~GCLK;

endmodule