syncprocessor.v

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`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    15:03:18 09/06/06
// Design Name:    
// Module Name:    SyncProcessor
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module SyncProcessor(Pixel_Clk, H_Act_Pixel, V_Act_Line ,H_Sync , V_Sync,Data_Enable);

parameter Count_Width = 10 ;
parameter HS_Width = 16 ;
parameter VS_Width = 5 ;	
parameter H_Total = 560 ;
parameter V_Total = 320 ;
parameter H_Active = 480 ;
parameter V_Active = 234 ;
parameter H_Start = 32 ;
parameter V_Start	= 10 ;

    input Pixel_Clk;
	 output H_Sync ;
	 output V_Sync ; 
	 output Data_Enable ;	
    output [Count_Width -1 :0] H_Act_Pixel;
    output [Count_Width -1 :0] V_Act_Line;

    wire [Count_Width -1 :0] H_Act_Pixel;
    wire [Count_Width -1 :0] V_Act_Line;
	  	
    reg [Count_Width -1 :0] H_Count;
    reg [Count_Width -1 :0] V_Count;

	assign H_Sync = (H_Count < HS_Width  ) ;
	assign V_Sync = (V_Count < VS_Width  ) ;
	assign Data_Enable = ( (H_Count >= H_Start) & (H_Count < H_Start + H_Active)  & (V_Count >= V_Start) & (V_Count < V_Start + V_Active) ) ;		
	assign H_Act_Pixel = H_Count - H_Start ; 
	assign V_Act_Line = V_Count -	V_Start ;


	always @ (posedge Pixel_Clk) 
	begin
		if (H_Count > H_Total  )
			H_Count = 0 ;
		else
			H_Count = H_Count +1 ;
	end

	always @ (posedge H_Sync) 
	begin
		if (V_Count > V_Total  )
			V_Count = 0 ;
		else			
			V_Count = V_Count +1 ;
	end


endmodule