teststatemachine_tb.v

FPGA 学习 .再学习 .谢谢!啥得啊,还不够呢!

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 7.1i
//  \   \         Application : ISE Foundation
//  /   /         Filename : TestStateMachine.tfw
// /___/   /\     Timestamp : Tue Oct 03 11:38:16 2006
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: 
//Design Name: TestStateMachine
//Device: Xilinx
//
`timescale 1ns/1ps

module TestStateMachine;
    reg CLK = 1'b0;
    reg CLK_H = 1'b0;
    reg [9:0] V_Line = 10'b0000000000;
    wire StateChangePulse;
    wire [1:0] MuxSel;
    wire [1:0] MuxSel2;

    parameter PERIOD_CLK = 300;
    parameter real DUTY_CYCLE_CLK = 0.5;
    parameter OFFSET_CLK = 0;
    parameter PERIOD_CLK_H = 40;
    parameter real DUTY_CYCLE_CLK_H = 0.5;
    parameter OFFSET_CLK_H = 0;

    initial    // Clock process for CLK
    begin
        #OFFSET_CLK;
        forever
        begin
            CLK = 1'b0;
            #(PERIOD_CLK-(PERIOD_CLK*DUTY_CYCLE_CLK)) CLK = 1'b1;
            #(PERIOD_CLK*DUTY_CYCLE_CLK);
        end
    end

    initial    // Clock process for CLK_H
    begin
        #OFFSET_CLK_H;
        forever
        begin
            CLK_H = 1'b0;
            #(PERIOD_CLK_H-(PERIOD_CLK_H*DUTY_CYCLE_CLK_H)) CLK_H = 1'b1;
            #(PERIOD_CLK_H*DUTY_CYCLE_CLK_H);
        end
    end

    StateMachine UUT (
        .CLK(CLK),
        .CLK_H(CLK_H),
        .V_Line(V_Line),
        .StateChangePulse(StateChangePulse),
        .MuxSel(MuxSel),
        .MuxSel2(MuxSel2));

    integer TX_FILE = 0;
    integer TX_ERROR = 0;
    
    initial begin  // Open the results file...
        TX_FILE = $fopen("results.txt");
        #10300 // Final time:  10300 ns
        if (TX_ERROR == 0) begin
            $display("No errors or warnings.");
            $fdisplay(TX_FILE, "No errors or warnings.");
        end else begin
            $display("%d errors found in simulation.", TX_ERROR);
            $fdisplay(TX_FILE, "%d errors found in simulation.", TX_ERROR);
        end
        $fclose(TX_FILE);
        $stop;
    end

    initial begin // Process for CLK
    end

    initial begin // Process for CLK_H
    end

    task CHECK_StateChangePulse;
        input NEXT_StateChangePulse;

        #0 begin
            if (NEXT_StateChangePulse !== StateChangePulse) begin
                $display("Error at time=%dns StateChangePulse=%b, expected=%b", $time, StateChangePulse, NEXT_StateChangePulse);
                $fdisplay(TX_FILE, "Error at time=%dns StateChangePulse=%b, expected=%b", $time, StateChangePulse, NEXT_StateChangePulse);
                $fflush(TX_FILE);
                TX_ERROR = TX_ERROR + 1;
            end
        end
    endtask
    task CHECK_MuxSel;
        input [1:0] NEXT_MuxSel;

        #0 begin
            if (NEXT_MuxSel !== MuxSel) begin
                $display("Error at time=%dns MuxSel=%b, expected=%b", $time, MuxSel, NEXT_MuxSel);
                $fdisplay(TX_FILE, "Error at time=%dns MuxSel=%b, expected=%b", $time, MuxSel, NEXT_MuxSel);
                $fflush(TX_FILE);
                TX_ERROR = TX_ERROR + 1;
            end
        end
    endtask
    task CHECK_MuxSel2;
        input [1:0] NEXT_MuxSel2;

        #0 begin
            if (NEXT_MuxSel2 !== MuxSel2) begin
                $display("Error at time=%dns MuxSel2=%b, expected=%b", $time, MuxSel2, NEXT_MuxSel2);
                $fdisplay(TX_FILE, "Error at time=%dns MuxSel2=%b, expected=%b", $time, MuxSel2, NEXT_MuxSel2);
                $fflush(TX_FILE);
                TX_ERROR = TX_ERROR + 1;
            end
        end
    endtask

endmodule