control.v

初学cpu设计（完全教程）包括verilog代码以及文档说明那个

module control(din,clk,rst,z,read,write,arload,arinc,pcinc,pcload,drload,trload,irload,rload,alus,acload,zload,pcbus,drhbus,drlbus,trbus,rbus,acbus,membus,busmem);
input [7:0]din;
input clk,rst,z;
output read,write,arload,arinc,pcinc,pcload,drload,trload,irload,rload,acload,zload,pcbus,drhbus,drlbus,trbus,rbus,acbus,membus,busmem;
output[6:0]alus;


//parameter's define

wire fetch1,fetch2,fetch3,nop1,ldac1,ldac2,ldac3,ldac4,ldac5,stac1,stac2,stac3,stac4,stac5,mvac1,movr1,jump1,jump2,jump3,jmpzy1,
	jmpzy2,jmpzy3,jmpzn1,jmpzn2,jpnzy1,jpnzy2,jpnzy3,jpnzn1,jpnzn2,add1,sub1,inac1,clac1,and1,or1,xor1,not1;

reg inop,ildac,istac,imvac,imovr,ijump,ijmpz,ijpnz,iadd,isub,iinac,iclac,iand,ior,ixor,inot;

reg t0,t1,t2,t3,t4,t5,t6,t7;

// signals for the counter, 
wire clr;
wire inc;
// assign signals for the cunter
assign clr=nop1||ldac5||stac5||mvac1||movr1||jump3||jmpzy3||jmpzn2||jpnzy3||jpnzn2||add1||sub1||inac1||clac1||and1||or1||xor1||not1;
assign inc=~clr;
	
//generate the control signal using state information
//...
assign fetch1=t0;
assign fetch2=t1;
assign fetch3=t2;
assign nop1=inop&&t3;
assign ldac1=ildac&&t3;
assign ldac2=ildac&&t4;
assign ldac3=ildac&&t5;
assign ldac4=ildac&&t6;
assign ldac5=ildac&&t7;

assign stac1=istac&&t3;
assign stac2=istac&&t4;
assign stac3=istac&&t5;
assign stac4=istac&&t6;
assign stac5=istac&&t7;

assign mvac1=imvac&&t3;
assign movr1=imovr&&t3;

assign jump1=ijump&&t3;
assign jump2=ijump&&t4;
assign jump3=ijump&&t5;

assign jmpzy1=ijmpz&&z&&t3;
assign jmpzy2=ijmpz&&z&&t4;
assign jmpzy3=ijmpz&&z&&t5;
assign jmpzn1=ijmpz&&(!z)&&t3;
assign jmpzn2=ijmpz&&(!z)&&t4;

assign jpnzy1=ijpnz&&(!z)&&t3;
assign jpnzy2=ijpnz&&(!z)&&t4;
assign jpnzy3=ijpnz&&(!z)&&t5;
assign jpnzn1=ijpnz&&z&&t3;
assign jpnzn2=ijpnz&&z&&t4;

assign add1=iadd&&t3;
assign sub1=isub&&t3;
assign inac1=iinac&&t3;
assign clac1=iclac&&t3;
assign and1=iand&&t3;
assign or1=ior&&t3;
assign xor1=ixor&&t3;
assign not1=inot&&t3;

//the next grade assign
assign read=fetch2||ldac1||ldac2||ldac4||stac1||stac2||jump1||jump2||jmpzy1||jmpzy2||jpnzy1||jpnzy2; 
assign pcbus=fetch1||fetch3;
assign drhbus=ldac3||stac3||jump3||jmpzy3||jpnzy3;
assign drlbus=ldac5||stac5;
assign trbus=ldac3||stac3||jump3||jmpzy3||jpnzy3;
assign rbus=movr1||add1||sub1||and1||or1||xor1;
assign acbus=stac4||mvac1;
assign membus=fetch2||ldac1||ldac2||ldac4||stac1||stac2||jump1||jump2||jmpzy1||jmpzy2||jpnzy1||jpnzy2;
assign busmem=stac5;
assign arload=fetch1||fetch3||ldac3||stac3;
assign arinc=ldac1||stac1||jump1||jmpzy1||jpnzy1;

assign pcload=jump3||jmpzy3||jpnzy3;
assign pcinc=fetch2||ldac1||ldac2||stac1||stac2||jmpzn1||jmpzn2||jpnzn1||jpnzn2;
assign drload=fetch2||ldac1||ldac2||ldac4||stac1||stac2||stac4||jump1||jump2||jmpzy1||jmpzy2||jpnzy1||jpnzy2;
assign trload=ldac2||stac2||jump2||jmpzy2||jpnzy2;
assign irload=fetch3;
assign rload=mvac1;
assign acload=ldac5||movr1||add1||sub1||inac1||clac1||and1||or1||xor1||not1;
assign zload=add1||sub1||inac1||clac1||and1||or1||xor1||not1;
assign write=stac5;

//assign the alusel signals
assign alus[0]=add1||sub1||inac1;
assign alus[1]=sub1;
assign alus[2]=ldac5||movr1||add1;
assign alus[3]=sub1||inac1;
assign alus[4]=xor1||not1;
assign alus[5]=or1||not1;
assign alus[6]=and1||or1||xor1||not1;

//the finite state

always@(posedge clk or negedge rst)
if(!rst)
	begin
	/* fetch1=0;
	 fetch2=0;
	 fetch3=0;
	 nop1=0;
	 ldac1=0;
	 ldac2=0;
	 ldac3=0;
	 ldac4=0;
	 ldac5=0;
	 stac1=0;
	 stac2=0;
	 stac3=0;
	 stac4=0;
	 stac5=0;
	 mvac1=0;
	 movr1=0;
	 jump1=0;
	 jump2=0;
	 jump3=0;
	 jmpzy1=0;
	jmpzy2=0;
	jmpzy3=0;
	jmpzn1=0;
	jmpzn2=0;
	jpnzy1=0;
	jpnzy2=0;
	jpnzy3=0;
	jpnzn1=0;
	jpnzn2=0;
	add1=0;
	sub1=0;
	inac1=0;
	clac1=0;
	or1=0;
	xor1=0;
	not1=0;
	
	alus=0;*/
		inop<=0;
		ildac<=0;
		istac<=0;
		imvac<=0;
		imovr<=0;
		ijump<=0;
		ijmpz<=0;
		ijpnz<=0;
		iadd<=0;
		isub<=0;
		iinac<=0;
		iclac<=0;
		iand<=0;
		ior<=0;
		ixor<=0;
		inot<=0;
		
	end
else if(din[7:4]==0000)
   	case(din[3:0])
	0:  begin
		inop<=1;
		ildac<=0;
		istac<=0;
		imvac<=0;
		imovr<=0;
		ijump<=0;
		ijmpz<=0;
		ijpnz<=0;
		iadd<=0;
		isub<=0;
		iinac<=0;
		iclac<=0;
		iand<=0;
		ior<=0;
		ixor<=0;
		inot<=0;
		end
	1:  begin
		inop<=0;
		ildac<=1;
		istac<=0;
		imvac<=0;
		imovr<=0;
		ijump<=0;
		ijmpz<=0;
		ijpnz<=0;
		iadd<=0;
		isub<=0;
		iinac<=0;
		iclac<=0;
		iand<=0;
		ior<=0;
		ixor<=0;
		inot<=0;
		end
	2:  begin
		inop<=0;
		ildac<=0;
		istac<=1;
		imvac<=0;
		imovr<=0;
		ijump<=0;
		ijmpz<=0;
		ijpnz<=0;
		iadd<=0;
		isub<=0;
		iinac<=0;
		iclac<=0;
		iand<=0;
		ior<=0;
		ixor<=0;
		inot<=0;
		end
	3:  begin
		inop<=0;
		ildac<=0;
		istac<=0;
		imvac<=1;
		imovr<=0;
		ijump<=0;
		ijmpz<=0;
		ijpnz<=0;
		iadd<=0;
		isub<=0;
		iinac<=0;
		iclac<=0;
		iand<=0;
		ior<=0;
		ixor<=0;
		inot<=0;
		end
	4:  begin
		inop<=0;
		ildac<=0;
		istac<=0;
		imvac<=0;
		imovr<=1;
		ijump<=0;
		ijmpz<=0;
		ijpnz<=0;
		iadd<=0;
		isub<=0;
		iinac<=0;
		iclac<=0;
		iand<=0;
		ior<=0;
		ixor<=0;
		inot<=0;
		end
	5:  begin
		inop<=0;
		ildac<=0;
		istac<=0;
		imvac<=0;
		imovr<=0;
		ijump<=1;
		ijmpz<=0;
		ijpnz<=0;
		iadd<=0;
		isub<=0;
		iinac<=0;
		iclac<=0;
		iand<=0;
		ior<=0;
		ixor<=0;
		inot<=0;
		end
	6:	begin
		inop<=0;
		ildac<=0;
		istac<=0;
		imvac<=0;
		imovr<=0;
		ijump<=0;
		ijmpz<=1;
		ijpnz<=0;
		iadd<=0;
		isub<=0;
		iinac<=0;
		iclac<=0;
		iand<=0;
		ior<=0;
		ixor<=0;
		inot<=0;
		end
	7:	begin
		inop<=0;
		ildac<=0;
		istac<=0;
		imvac<=0;
		imovr<=0;
		ijump<=0;
		ijmpz<=0;
		ijpnz<=1;
		iadd<=0;
		isub<=0;
		iinac<=0;
		iclac<=0;
		iand<=0;
		ior<=0;
		ixor<=0;
		inot<=0;
		end
	8:	begin
		inop<=0;
		ildac<=0;
		istac<=0;
		imvac<=0;
		imovr<=0;
		ijump<=0;
		ijmpz<=0;
		ijpnz<=0;
		iadd<=1;
		isub<=0;
		iinac<=0;
		iclac<=0;
		iand<=0;
		ior<=0;
		ixor<=0;
		inot<=0;
		end
	9:	begin
		inop<=0;
		ildac<=0;
		istac<=0;
		imvac<=0;
		imovr<=0;
		ijump<=0;
		ijmpz<=0;
		ijpnz<=0;
		iadd<=0;
		isub<=1;
		iinac<=0;
		iclac<=0;
		iand<=0;
		ior<=0;
		ixor<=0;
		inot<=0;
		end
	10:	begin
		inop<=0;
		ildac<=0;
		istac<=0;
		imvac<=0;
		imovr<=0;
		ijump<=0;
		ijmpz<=0;
		ijpnz<=0;
		iadd<=0;
		isub<=0;
		iinac<=1;
		iclac<=0;
		iand<=0;
		ior<=0;
		ixor<=0;
		inot<=0;
		end
	11:	begin
		inop<=0;
		ildac<=0;
		istac<=0;
		imvac<=0;
		imovr<=0;
		ijump<=0;
		ijmpz<=0;
		ijpnz<=0;
		iadd<=0;
		isub<=0;
		iinac<=0;
		iclac<=1;
		iand<=0;
		ior<=0;
		ixor<=0;
		inot<=0;
		end
	12:	begin
		inop<=0;
		ildac<=0;
		istac<=0;
		imvac<=0;
		imovr<=0;
		ijump<=0;
		ijmpz<=0;
		ijpnz<=0;
		iadd<=0;
		isub<=0;
		iinac<=0;
		iclac<=0;
		iand<=1;
		ior<=0;
		ixor<=0;
		inot<=0;
		end
	13:	begin
		inop<=0;
		ildac<=0;
		istac<=0;
		imvac<=0;
		imovr<=0;
		ijump<=0;
		ijmpz<=0;
		ijpnz<=0;
		iadd<=0;
		isub<=0;
		iinac<=0;
		iclac<=0;
		iand<=0;
		ior<=1;
		ixor<=0;
		inot<=0;
		end
	14:	begin
		inop<=0;
		ildac<=0;
		istac<=0;
		imvac<=0;
		imovr<=0;
		ijump<=0;
		ijmpz<=0;
		ijpnz<=0;
		iadd<=0;
		isub<=0;
		iinac<=0;
		iclac<=0;
		iand<=0;
		ior<=0;
		ixor<=1;
		inot<=0;
		end
	15:	begin
		inop<=0;
		ildac<=0;
		istac<=0;
		imvac<=0;
		imovr<=0;
		ijump<=0;
		ijmpz<=0;
		ijpnz<=0;
		iadd<=0;
		isub<=0;
		iinac<=0;
		iclac<=0;
		iand<=0;
		ior<=0;
		ixor<=0;
		inot<=1;
	end	
endcase
always @(posedge clk or negedge rst)
if(!rst)
	begin
	t0<=1;
	t1<=0;
	t2<=0;
	t3<=0;
	t4<=0;
	t5<=0;
	t6<=0;
	t7<=0;
	end
else if(clr)
	begin 
	t0<=1;
	t1<=0;
	t2<=0;
	t3<=0;
	t4<=0;
	t5<=0;
	t6<=0;
	t7<=0;
	end
else if(inc)
	begin
	t7<=t6;
	t6<=t5;
	t5<=t4;
	t4<=t3;
	t3<=t2;
	t2<=t1;
	t1<=t0;
	t0<=0;
	end
endmodule