cpu.v.bak

初学cpu设计（完全教程）包括verilog代码以及文档说明那个

//the very simple cpu
//design by zhxj,2005.4

module simplecpu(din,rst, clk, read, dout);
input [7:0]din;
input rst, clk;
output read;
output [5:0]dout;

wire [1:0]irout;	 
wire [5:0]dout,pcdbus;
wire [7:0] dbus;
wire[7:0] aluout;
wire[7:0] ac,drdbus;
wire arload, pcload, pcinc,pcbus,drbus,membus, drload, acload, acinc, alusel, irload;
ar mar(dbus[5:0],rst,arload, clk, dout);
pc mpc(dbus[5:0],clk, rst, pcload, pcinc, pcdbus[5:0]);
dr mdr(dbus,clk, rst, drload, drdbus);
ac mac(aluout,clk, rst, acload,acinc,ac);
alu malu(ac, dbus, alusel, aluout);
ir mir(dbus[7:6],clk, rst, irload, irout);
control mcontrol(irout, clk, rst, arload, pcload, pcinc, drload, acload, acinc, irload, alusel, membus, pcbus, drbus, read); 
//assign dbus[5:0]=(pcbus)?pcdbus[5:0]:dbus[5:0];
//assign dbus=(drbus)?drdbus:dbus;	
//assign dbus=(membus)?din:dbus;  
 			  assign dbus[5:0]=(pcbus)?pcdbus[5:0]:6'bzzzzzz;
             assign dbus=(drbus)?drdbus:8'bzzzzzzzz;	
               assign dbus=(membus)?din:8'bzzzzzzzz;  
endmodule