ahb_master.vhd

来自「vhdl实现的amba代码」· VHDL 代码 · 共 688 行 · 第 1/2 页

--*******************************************************************
--**                                                             ****
--**  AHB system generator                                       ****
--**                                                             ****
--**  Author: Federico Aglietti                                  ****
--**          federico.aglietti\@opencores.org                   ****
--**                                                             ****
--*******************************************************************
--**                                                             ****
--** Copyright (C) 2004 Federico Aglietti                        ****
--**                    federico.aglietti\@opencores.org         ****
--**                                                             ****
--** This source file may be used and distributed without        ****
--** restriction provided that this copyright statement is not   ****
--** removed from the file and that any derivative work contains ****
--** the original copyright notice and the associated disclaimer.****
--**                                                             ****
--**     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ****
--** EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ****
--** TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ****
--** FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ****
--** OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ****
--** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ****
--** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ****
--** GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ****
--** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ****
--** LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ****
--** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ****
--** OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ****
--** POSSIBILITY OF SUCH DAMAGE.                                 ****
--**                                                             ****
--*******************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;

use work.ahb_funct.all;
use work.ahb_package.all;

entity ahb_master is
generic (
  fifohempty_level: in integer:= 2;
  fifohfull_level: in integer:= 6;
  fifo_length: in integer:= 8);
port (
  --***********************************************
  --master ahb amba signals
  --***********************************************	 
  hresetn: in std_logic;
  hclk: in std_logic;
  mst_in: in mst_in_t;
  mst_out: out mst_out_t;
 
  --***********************************************
  --master<=>core interface: conf registers
  --***********************************************
  dma_start: in start_type_t;	   
 
  --***********************************************
  --master<=>core interface: program/data memories 
  --***********************************************
  m_wrap_out: out wrap_out_t;
  m_wrap_in: in wrap_in_t;   

   --***********************************************
  --master/slave/core signals
  --***********************************************
  slv_running: in std_logic;
  mst_running: out std_logic;
  eot_int: out std_logic
  );
end ahb_master;

architecture rtl of ahb_master is

--***************************************************************
--component declaration 
--***************************************************************
component fifo
generic (
  fifohempty_level: in integer:= 1;
  fifohfull_level: in integer:= 7;
  fifo_length: in integer:= 8);
port (
  hresetn: in std_logic;
  clk: in std_logic;
  fifo_reset: in std_logic;
  fifo_write: in std_logic;
  fifo_read: in std_logic;
  fifo_count: out std_logic_vector(nb_bits(fifo_length)-1 downto 0);  
  fifo_full: out std_logic;
  fifo_hfull: out std_logic;
  fifo_empty: out std_logic;
  fifo_hempty: out std_logic;
  fifo_datain: in std_logic_vector(31 downto 0);
  fifo_dataout: out std_logic_vector(31 downto 0)
  );
end component;


 
--***************************************************************
--configuration registers 
--***************************************************************
signal start_hprot: std_logic_vector(3 downto 0);
signal start_hsize: std_logic_Vector(2 downto 0);
signal start_hburst: std_logic_Vector(2 downto 0);
signal start_hwrite: std_logic;
signal start_hlocked: std_logic;
signal start_prior: std_logic;

signal hbusreq_t, hlock_t: std_logic;
--***************************************************************
--***************************************************************
signal r_mst_in, s_mst_in: mst_in_t;
signal r_mst_out, s_mst_out: mst_out_t;


type master_fsm is (
  idle_phase,
  wait_phase,   
  req_phase,
  addr,     --A
  addr_data,--A+D
  data,	    --D
  retry_phase, 
  error_phase,
  be_phase);
signal mst_state, s_mst_state: master_fsm;


signal fifo_full, fifo_hfull, fifo_empty, fifo_hempty: std_logic;
signal fifo_count: std_logic_vector(nb_bits(fifo_length)-1 downto 0);  
signal fifo_datain, fifo_dataout: std_logic_vector (31 downto 0);
signal fifo_hread, fifo_hwrite: std_logic;
signal fifo_read, fifo_write: std_logic;
signal fifo_reset: std_logic;
signal next_fifo_empty: std_logic;

signal dma_count: std_logic_vector (15 downto 0);
signal dma_count_s : std_logic_vector (15 downto 0);
signal right_count: std_logic_vector(15 downto 0);
signal data_trx: std_logic;  
signal tmp_htrans: std_logic_vector(1 downto 0);


signal next_fifo_full: std_logic;
signal next_fifo_he: std_logic;
signal next_fifo_hf: std_logic;

signal mst_running_t:std_logic;
signal dma_restart: std_logic;
signal mst_req: std_logic;
signal granted: std_logic;

signal eot_int_reg:std_logic;
signal prior_reg, prior_s: std_logic;

signal int_addr, int_addr_s, int_addr_t : std_logic_vector (31 downto 0);
signal int_mod, int_mod_s : std_logic_vector (15 downto 0);
signal int_page_fault: std_logic;
signal int_addr_incr: std_logic;

signal page_attention: std_logic;
signal page_fault: std_logic;
signal pf_incr, pf_wrap4, pf_wrap8, pf_wrap16: std_logic;

signal haddr_t : std_logic_vector (31 downto 0);
signal haddr_incr: std_logic;

signal old_page_attention: std_logic;
signal old_addr_incr: std_logic;
signal old_addr, old_addr_s: std_logic_vector (31 downto 0);
signal old_hburst, old_hburst_s: std_logic_Vector(2 downto 0);

begin

--***************************************************************
--component instantiation 
--***************************************************************
fifo_inst: fifo
generic map(
  fifohempty_level => fifohempty_level,
  fifohfull_level => fifohfull_level,
  fifo_length => fifo_length)
port map(
  hresetn => hresetn,
  clk => hclk,
  fifo_reset =>	fifo_reset,
  fifo_write =>	fifo_write,
  fifo_read => fifo_read,
  fifo_count => fifo_count,
  fifo_full => fifo_full,
  fifo_hfull => fifo_hfull,
  fifo_empty => fifo_empty,
  fifo_hempty => fifo_hempty,
  fifo_datain => fifo_datain,
  fifo_dataout => fifo_dataout
  );
	
	
--***************************
--****** master state *******
--***************************	
master_pr:process(
mst_state,
mst_req,
slv_running,
prior_reg,
dma_count,
hbusreq_t,
fifo_empty,
page_fault,
r_mst_out,
mst_in
)
begin
  s_mst_state <= mst_state;	
  case mst_state is
    when idle_phase =>
      if (dma_count>0 and (slv_running='0' or prior_reg=master)) then
        s_mst_state <= wait_phase;
      end if;
    when wait_phase =>
      if mst_req='1' then
        s_mst_state <= req_phase;	
      end if;	
    when req_phase =>
      if (hbusreq_t='1' and mst_in.hgrant='1' and mst_in.hready='1') then--master take bus ownership
        s_mst_state <= addr;
      end if;
    when addr =>
      if (mst_in.hready='1') then
        if (page_fault='1' or mst_in.hgrant='0' or dma_count=1) then
          s_mst_state <= data;
        else
          s_mst_state <= addr_data;
        end if;
      end if;
    when addr_data =>
      --end of transfer: ready+ok+no_busy_reg+count=1(idle/preidle or burstend)
      --page fault:ready+ok+no_busy_reg+count>1	(page_fault)
      --no_grant:ready+ok+busy+no_grant (page_fault)
      --retry/split:no_ready+retry/split (retry)
      --error:no_ready+error (error)
      if (mst_in.hready='1') then
        if (mst_in.hresp=ok_resp) then 
          if (r_mst_out.htrans/=busy) then	
            if (dma_count=1) then
              if (r_mst_out.hwrite='1') then
                s_mst_state <= data;
              else --r_mst_out.hwrite='0', count>1
                s_mst_state <= data;--be_phase;
              end if; 
            elsif (page_fault='1' or mst_in.hgrant='0') then
              s_mst_state <= data;
            end if;
          else -- r_mst_out.htrans=busy
            if (mst_in.hgrant='0') then
	      assert false report "Protocol error: GRANT deasserted during BUSY!!!" severity error;
              s_mst_state <= data;
            end if;
          end if;
        end if;
      else--hready='0'	  
        case mst_in.hresp is
          when retry_resp|split_resp =>
            s_mst_state <= retry_phase;
          when error_resp =>
            s_mst_state <= error_phase;
          when others =>
            s_mst_state <= addr_data;
        end case;
      end if;
    when data=>
      if (mst_in.hready='1') then
        if (mst_in.hresp=ok_resp and r_mst_out.htrans/=busy) then
          if (dma_count=0) then
            if (r_mst_out.hwrite='1') then
              s_mst_state <= idle_phase;
            else --r_mst_out.hwrite='0', count>1
              s_mst_state <= be_phase;
            end if;
          else--collapse all this 'if-else'
            if (r_mst_out.hwrite='1') then
              s_mst_state <= idle_phase;
            else
              s_mst_state <= be_phase;
            end if;
          end if;				  
        end if;
      else	  
        case mst_in.hresp is
          when retry_resp|split_resp =>
            s_mst_state <= retry_phase;--pay attention: grant removed and retry issued!!!!!!
          when error_resp =>
            s_mst_state <= error_phase;
          when others =>
            s_mst_state <= data;
        end case;
      end if;	  
    when retry_phase =>
      if (mst_in.hready='1') then
          s_mst_state <= idle_phase;
      end if;
    when error_phase =>
      if mst_in.hready='1' then
        s_mst_state <= idle_phase;
      end if;
    when be_phase =>--one of more cycle to empty fifo, settling core internal state
      if (fifo_empty ='1') then
        s_mst_state <= idle_phase;
      end if;
    when others => null;
  end case;
end process;

--synopsys translate_off
assert not (hclk'event and hclk='1' and (mst_state=addr_data or mst_state=data) and (mst_in.hready='1' and mst_in.hresp/=ok_resp)) 
report "####PROTOCOL ERROR: in addr_data error/retry/split&&ready!!!!!"
severity error;
--synopsys translate_on

process(hresetn, hclk)
begin
  if hresetn='0' then
    mst_state <= idle_phase;
  elsif hclk'event and hclk='1' then
    mst_state <= s_mst_state after 1 ns;
  end if;
end process;
	  

start_hlocked <= dma_start.hparams(0);
start_hwrite <= dma_start.hparams(1);
start_hprot <= dma_start.hparams(5 downto 2);
start_hburst <= dma_start.hparams(8 downto 6);
start_hsize <= dma_start.hparams(11 downto 9);
start_prior <= dma_start.hparams(12);

--***************************