ahb_arbiter.vhd

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  s_seed(0) <= not(seed(9) xor seed(6));
end process;	   	  

seed_pr:process(hresetn, hclk)
variable v_random: integer range 0 to 2**(nb_bits(num_arb_msts));
begin
  if hresetn='0' then
    seed <= (others => '0');--"1101010001";
    random <= 0;
    --synopsys translate_off
    for i in 0 to 2**(nb_bits(num_arb_msts)) loop
      vect_ran(i) <= 0;
      vect_ran_round(i) <= 0;
    end loop;
    --synopsys translate_on
  elsif hclk'event and hclk='1' then
    seed <= s_seed after 1 ns;
    v_random := conv_integer(seed(nb_bits(num_arb_msts)+3 downto 4));
    if v_random < num_arb_msts then
      random <= v_random after 1 ns; 
    else
      random <= turn after 1 ns;--(v_random - num_arb_msts);
    end if;
    --synopsys translate_off
    vect_ran(v_random) <= vect_ran(v_random) + 1;
    vect_ran_round(random) <= vect_ran_round(random) + 1;
    --synopsys translate_on
  end if;
end process;



--synopsys translate_off
  assert not (hclk'event and hclk='1' and master_sel=num_arb_msts) report "DUMMY MASTER selection!!!" severity WARNING;
  assert not (hclk'event and hclk='1' and master_sel=def_arb_mst) report "DEFAULT MASTER selection!!!" severity WARNING;
  assert not (hclk'event and hclk='1' and (master_sel>num_arb_msts or r_master_sel>num_arb_msts)) report "####ERROR in MASTER selection!!!" severity FAILURE;
--synopsys translate_on


--*********************************************************
-- MASTER MUXES
--*********************************************************

add_pr:process(master_sel, r_master_sel, mst_in_v)
variable def_addr: std_logic_vector(31 downto 0);
begin

  haddr_page(31 downto 10) <= mst_in_v(def_arb_mst).haddr(31 downto 10);

  mst_in_sel.hwdata <= mst_in_v(def_arb_mst).hwdata;
  mst_in_sel.haddr <= mst_in_v(def_arb_mst).haddr;
  mst_in_sel.hwrite <= mst_in_v(def_arb_mst).hwrite;
  mst_in_sel.hsize <= mst_in_v(def_arb_mst).hsize;
  mst_in_sel.hburst <= mst_in_v(def_arb_mst).hburst;
  mst_in_sel.hprot <= mst_in_v(def_arb_mst).hprot;
  mst_in_sel.htrans <= mst_in_v(def_arb_mst).htrans;
  for i in 0 to num_arb_msts-1 loop 
    if i=conv_integer(r_master_sel) then
      mst_in_sel.hwdata <= mst_in_v(i).hwdata;
    end if;
    if i=conv_integer(master_sel) then
      haddr_page(31 downto 10) <= mst_in_v(i).haddr(31 downto 10);
      mst_in_sel.haddr <= mst_in_v(i).haddr;
      mst_in_sel.hwrite <= mst_in_v(i).hwrite;
      mst_in_sel.hsize <= mst_in_v(i).hsize;
      mst_in_sel.hburst <= mst_in_v(i).hburst;
      mst_in_sel.hprot <= mst_in_v(i).hprot;
      mst_in_sel.htrans <= mst_in_v(i).htrans;
    end if;	
  end loop;
  if master_sel=num_arb_msts then
    mst_in_sel.htrans <= idle;
  end if;	  
end process;  

process(slv_in_sel, s_grant_master)--N.B.: Request=>Grant comb. path!
begin										   
  for i in 0 to num_arb_msts-1 loop 
    mst_out_v(i).hready <= slv_in_sel.hready;
    mst_out_v(i).hresp <= slv_in_sel.hresp;
    mst_out_v(i).hrdata <= slv_in_sel.hrdata;
    if (s_grant_master=i) then
      mst_out_v(i).hgrant <= '1';
    else
      mst_out_v(i).hgrant <= '0';
    end if;
  end loop;
end process;

--*********************************************************
-- SLAVE MUXES
--*********************************************************

process(hresetn, hclk)
variable v_hready: std_logic;
begin				 
  if hresetn='0' then
    for i in num_slvs-1 downto 0 loop
      r_slv_in_v(i).hsel <= '0';
    end loop;  
  elsif hclk='1' and hclk'event then
    if s_dec_hready='1' then
	  r_def_slave_hsel <= def_slave_hsel;
      for i in num_slvs-1 downto 0 loop
        r_slv_in_v(i).hsel <= hsel(i) after 1 ns;
      end loop;
    end if;
  end if;  
end process;

process(r_slv_in_v, slv_in_v, def_slave_hready)
begin
  s_dec_hready <= def_slave_hready;
  for i in num_slvs-1 downto 0 loop
    if(r_slv_in_v(i).hsel='1') then
      s_dec_hready <= slv_in_v(i).hready;
	end if;	  
  end loop;  
--  hready_t <= slv_in_v(num_slvs).hready;--ready ....
  slv_in_sel.hready <= def_slave_hready;	 
  slv_in_sel.hrdata <= (others => '-');--for LOW POWER!!!
  slv_in_sel.hresp <= error_resp;--.... and ERROR ....		
  for i in num_slvs-1 downto 0 loop
    if r_slv_in_v(i).hsel='1' then
--      hready_t <= slv_in_v(i).hready;
      slv_in_sel.hready <= slv_in_v(i).hready;	 
      slv_in_sel.hresp <= slv_in_v(i).hresp;
      slv_in_sel.hrdata <= slv_in_v(i).hrdata;
    end if;
  end loop;
end process;


--*********************************************************
-- SPLIT handling
--*********************************************************

process(hresetn, hclk)
variable v_split_reg: std_logic_vector(num_arb_msts-1 downto 0);
begin
  if hresetn='0' then
    split_reg <= (others => '0');  
  elsif hclk'event and hclk='1' then
    v_split_reg := split_reg;
    for j in num_slvs-1 downto 0 loop
      for i in num_arb_msts-1 downto 0 loop
        v_split_reg(i) := v_split_reg(i) and not slv_in_v(j).hsplit(i); 
      end loop;
      if (r_slv_in_v(j).hsel='1') then
        if (slv_in_v(j).hready='1' and slv_in_v(j).hresp=split_resp and master_sel/=num_arb_msts) then
          v_split_reg(conv_integer(master_sel)) := '1';
        end if;
      end if;
    end loop;
    split_reg <= v_split_reg after 1 ns;	
  end if;
end process;

--*********************************************************
-- AHB DECODER
--*********************************************************
-- min 1KB of address space for each slave:
process(haddr_page, master_sel, mst_in_v, mst_in_sel, s_dec_hready, addr_arb_matrix)
  variable addr_low_std : std_logic_vector(31 downto 0);
  variable addr_high_std : std_logic_vector(31 downto 0);
  variable v_hmastlock: std_logic;
begin
  v_hmastlock := '0';
  for i in num_arb_msts-1 downto 0 loop
    if (v_hmastlock='0' and master_sel=conv_std_logic_Vector(i,4) and mst_in_v(i).hlock='1') then
      v_hmastlock := '1';
    end if;
  end loop;
  def_slave_hsel <= '1'; --default slave selected
  for i in num_slvs-1 downto 0 loop
    slv_out_v(i).hmastlock <= v_hmastlock;
    slv_out_v(i).haddr <= mst_in_sel.haddr;
    slv_out_v(i).hmaster <= master_sel;
    slv_out_v(i).hready <= s_dec_hready;
    slv_out_v(i).hwrite <= mst_in_sel.hwrite;
    slv_out_v(i).hwdata <= mst_in_sel.hwdata;
    slv_out_v(i).hsize <= mst_in_sel.hsize;
    slv_out_v(i).hburst <= mst_in_sel.hburst;
    slv_out_v(i).hprot <= mst_in_sel.hprot;
    slv_out_v(i).htrans <= mst_in_sel.htrans;
    addr_low_std := conv_std_logic_vector(addr_arb_matrix(0)(i).low, 32);
    addr_high_std := conv_std_logic_vector(addr_arb_matrix(0)(i).high, 32);
    if (haddr_page(31 downto 10) >= addr_low_std(31 downto 10) and (haddr_page(31 downto 10) <= addr_high_std(31 downto 10))) then
      hsel(i) <= '1';
      def_slave_hsel <= '0';	
      slv_out_v(i).hsel <= '1';
    else
      hsel(i) <= '0';
      slv_out_v(i).hsel <= '0';
    end if;	 
  end loop;  
end process;  


--DEFAULT SLAVE BEHAVIOUR

process(hresetn, hclk)
begin		   
  if hresetn='0' then
    def_slave_hready <= '1';
  elsif hclk'event and hclk='1' then
    if (def_slave_hsel='1' and s_dec_hready='1' and mst_in_sel.htrans/=idle) then
      def_slave_hready <= '0' after 1 ns;
    else
      def_slave_hready <= '1' after 1 ns;
    end if;
  end if;
end process;	



--synopsys translate_off
 assert not(hclk'event and hclk='1' and r_def_slave_hsel='1') report "####ERROR: NO SLAVE SELECTED!!!" severity error;
--synopsys translate_on

end rtl;