prev_cmp_taxi.tan.qmsg

在Quatus下用VerilogHDL语言编写

{ "Info" "ITDB_FULL_TCO_RESULT" "f64 min1\[2\] lpm_counter:min1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[2\] 18.000 ns register " "Info: tco from clock \"f64\" to destination pin \"min1\[2\]\" through register \"lpm_counter:min1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[2\]\" is 18.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f64 source 5.300 ns + Longest register " "Info: + Longest clock path from clock \"f64\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns f64 1 CLK PIN_43 50 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 50; CLK Node = 'f64'" {  } { { "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { f64 } "NODE_NAME" } } { "taxi.v" "" { Text "F:/my taxi/taxi.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns lpm_counter:min1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[2\] 2 REG LC2_B12 5 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC2_B12; Fanout = 5; REG Node = 'lpm_counter:min1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[2\]'" {  } { { "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { f64 lpm_counter:min1_rtl_2|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "f:/my software/quartus/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { f64 lpm_counter:min1_rtl_2|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } } { "f:/my software/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/my software/quartus/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { f64 f64~out lpm_counter:min1_rtl_2|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "f:/my software/quartus/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.600 ns + Longest register pin " "Info: + Longest register to pin delay is 11.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:min1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[2\] 1 REG LC2_B12 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_B12; Fanout = 5; REG Node = 'lpm_counter:min1_rtl_2\|alt_counter_f10ke:wysi_counter\|q\[2\]'" {  } { { "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:min1_rtl_2|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "f:/my software/quartus/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 4.000 ns min1\[2\]~227 2 COMB LC3_B7 1 " "Info: 2: + IC(2.200 ns) + CELL(1.800 ns) = 4.000 ns; Loc. = LC3_B7; Fanout = 1; COMB Node = 'min1\[2\]~227'" {  } { { "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { lpm_counter:min1_rtl_2|alt_counter_f10ke:wysi_counter|q[2] min1[2]~227 } "NODE_NAME" } } { "taxi.v" "" { Text "F:/my taxi/taxi.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(5.100 ns) 11.600 ns min1\[2\] 3 PIN PIN_28 0 " "Info: 3: + IC(2.500 ns) + CELL(5.100 ns) = 11.600 ns; Loc. = PIN_28; Fanout = 0; PIN Node = 'min1\[2\]'" {  } { { "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "7.600 ns" { min1[2]~227 min1[2] } "NODE_NAME" } } { "taxi.v" "" { Text "F:/my taxi/taxi.v" 88 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.900 ns ( 59.48 % ) " "Info: Total cell delay = 6.900 ns ( 59.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.700 ns ( 40.52 % ) " "Info: Total interconnect delay = 4.700 ns ( 40.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "11.600 ns" { lpm_counter:min1_rtl_2|alt_counter_f10ke:wysi_counter|q[2] min1[2]~227 min1[2] } "NODE_NAME" } } { "f:/my software/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/my software/quartus/quartus/bin/Technology_Viewer.qrui" "11.600 ns" { lpm_counter:min1_rtl_2|alt_counter_f10ke:wysi_counter|q[2] min1[2]~227 min1[2] } { 0.000ns 2.200ns 2.500ns } { 0.000ns 1.800ns 5.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { f64 lpm_counter:min1_rtl_2|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } } { "f:/my software/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/my software/quartus/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { f64 f64~out lpm_counter:min1_rtl_2|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } { "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "11.600 ns" { lpm_counter:min1_rtl_2|alt_counter_f10ke:wysi_counter|q[2] min1[2]~227 min1[2] } "NODE_NAME" } } { "f:/my software/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/my software/quartus/quartus/bin/Technology_Viewer.qrui" "11.600 ns" { lpm_counter:min1_rtl_2|alt_counter_f10ke:wysi_counter|q[2] min1[2]~227 min1[2] } { 0.000ns 2.200ns 2.500ns } { 0.000ns 1.800ns 5.100ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "cha2\[1\]~reg0 reset f64 1.000 ns register " "Info: th for register \"cha2\[1\]~reg0\" (data pin = \"reset\", clock pin = \"f64\") is 1.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "f64 destination 5.300 ns + Longest register " "Info: + Longest clock path from clock \"f64\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns f64 1 CLK PIN_43 50 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 50; CLK Node = 'f64'" {  } { { "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { f64 } "NODE_NAME" } } { "taxi.v" "" { Text "F:/my taxi/taxi.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns cha2\[1\]~reg0 2 REG LC3_C13 6 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_C13; Fanout = 6; REG Node = 'cha2\[1\]~reg0'" {  } { { "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { f64 cha2[1]~reg0 } "NODE_NAME" } } { "taxi.v" "" { Text "F:/my taxi/taxi.v" 88 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { f64 cha2[1]~reg0 } "NODE_NAME" } } { "f:/my software/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/my software/quartus/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { f64 f64~out cha2[1]~reg0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "taxi.v" "" { Text "F:/my taxi/taxi.v" 88 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns reset 1 PIN PIN_84 39 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_84; Fanout = 39; PIN Node = 'reset'" {  } { { "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "taxi.v" "" { Text "F:/my taxi/taxi.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.200 ns) 5.900 ns cha2\[1\]~reg0 2 REG LC3_C13 6 " "Info: 2: + IC(1.900 ns) + CELL(1.200 ns) = 5.900 ns; Loc. = LC3_C13; Fanout = 6; REG Node = 'cha2\[1\]~reg0'" {  } { { "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { reset cha2[1]~reg0 } "NODE_NAME" } } { "taxi.v" "" { Text "F:/my taxi/taxi.v" 88 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 67.80 % ) " "Info: Total cell delay = 4.000 ns ( 67.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns ( 32.20 % ) " "Info: Total interconnect delay = 1.900 ns ( 32.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { reset cha2[1]~reg0 } "NODE_NAME" } } { "f:/my software/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/my software/quartus/quartus/bin/Technology_Viewer.qrui" "5.900 ns" { reset reset~out cha2[1]~reg0 } { 0.000ns 0.000ns 1.900ns } { 0.000ns 2.800ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { f64 cha2[1]~reg0 } "NODE_NAME" } } { "f:/my software/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/my software/quartus/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { f64 f64~out cha2[1]~reg0 } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } { "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/my software/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { reset cha2[1]~reg0 } "NODE_NAME" } } { "f:/my software/quartus/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/my software/quartus/quartus/bin/Technology_Viewer.qrui" "5.900 ns" { reset reset~out cha2[1]~reg0 } { 0.000ns 0.000ns 1.900ns } { 0.000ns 2.800ns 1.200ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "106 " "Info: Allocated 106 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jul 01 15:51:52 2007 " "Info: Processing ended: Sun Jul 01 15:51:52 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}