de_pl_mpsk.hier_info

基于VHDL硬件描述语言

|de_PL_MPSK
clk => q[2].CLK
clk => q[1].CLK
clk => q[0].CLK
clk => yy[2].CLK
clk => yy[1].CLK
clk => yy[0].CLK
clk => y~reg0.CLK
clk => xx[2].CLK
clk => xx[1].CLK
clk => xx[0].CLK
clk => yyy[1].CLK
clk => yyy[0].CLK
start => q~14.OUTPUTSELECT
start => q~13.OUTPUTSELECT
start => q~12.OUTPUTSELECT
start => xx[0].ENA
start => xx[1].ENA
start => xx[2].ENA
start => y~reg0.ENA
start => yy[0].ENA
start => yy[1].ENA
start => yy[2].ENA
x => xx~3.OUTPUTSELECT
x => xx~4.OUTPUTSELECT
x => xx~19.DATAB
x => xx~0.OUTPUTSELECT
x => xx~1.OUTPUTSELECT
x => xx~2.OUTPUTSELECT
x => xx~7.OUTPUTSELECT
x => xx~6.OUTPUTSELECT
x => xx~5.OUTPUTSELECT
y <= y~reg0.DB_MAX_OUTPUT_PORT_TYPE