pwm.txt

自己写的一个pwm模块

module PWM(clk,addr,wr_n,wrdata,reset,pwm1,pwm2,pwm3,pwm4);
input clk,wr_n,reset; //wr_n ----- 写有效，在SOPC Builder中设为wr_n
                      //reset ----  全局复位信号，低电平有效，在SOPC中设为reset_n信号
input [1:0]addr; //addr ----- 写地址，在SOPC Builder中设为address
input [15:0]wrdata;  //wrdata ----- 写数据线，16位，在SOPC Builder中设为writedata
output pwm1,pwm2,pwm3,pwm4; //这四个信号为输出信号，与H桥的1～4号开关管一一对应，适用于驱动
                         //4个NMOS构成的H桥，如果H桥上臂为PMOS，则PWM1和PWM2极性需要经过
                        // 非门方向，

reg [15:0]duty; //占空比
reg [15:0]period; //周期
reg [15:0]counter; //计数器
reg start;
reg out;
reg direct;
reg pwm1,pwm2,pwm3,pwm4;



always @(posedge clk or negedge reset)
begin
    if (reset == 1'b0)
    begin
     			duty[15:0] <= 16'h7fff;
			{direct,start} <= 2'b00;
			period[15:0] <= 16'h0ffff;
    end 
    else
    begin  
       if (wr_n == 1'b0)
       begin
           
          if (addr[1:0] == 2'b00) 
		    begin
			   {direct,start} <= wrdata[1:0];
			   period[15:0] <= period[15:0];
			   duty[15:0] <= duty[15:0];
		    end

          else if (addr[1:0] == 2'b01) 
		    begin
			   start <= start;
			   direct <= direct;
			   period[15:0] <= wrdata[15:0];
			   duty[15:0] <= duty[15:0];
		    end
		    
          else if (addr[1:0] == 2'b10) 
		    begin
			   duty[15:0] <= wrdata[15:0];
			   start <= start;
			   direct <= direct;
			   period[15:0] <= period[15:0];
		    end
		    
		    else
		    begin
			   duty[15:0] <= duty[15:0];
			   start <= start;
			   direct <= direct;
			   period[15:0] <= period[15:0];
		    end	
    
       end
	    else
	    begin
		   duty[15:0] <= duty[15:0];
		   start <= start;
		   direct <= direct;
		   period[15:0] <= period[15:0];
	    end
   end   
end

always @(posedge clk)
begin
    
    if ((wr_n == 1'b0) && (addr[1:0] == 2'b11)) 
    begin
       counter[15:0] <= wrdata[15:0];
    end
    else if (start == 1'b1)
    begin
        if (counter[15:0] < period[15:0]) counter[15:0] <= counter[15:0] + 16'b1;
        else counter[15:0] <= 16'b0;
    end
    else counter[15:0] <= counter[15:0];
    
    if (start == 1'b1)
    begin
       if (counter[15:0] <= duty[15:0]) out <= 1'b1;
       else out <= 1'b0;
   end
   else out <= 1'b0;
end

always @(out or start or direct)
begin
    if (start == 1'b0)
    begin
        pwm1 = 1'b0;
        pwm2 = 1'b0;
        pwm3 = 1'b0;
        pwm4 = 1'b0;
    end
    else if (direct == 1'b0) 
    begin
        pwm1 = 1'b1;
        pwm2 = 1'b0;
        pwm3 = out;
        pwm4 = 1'b0;
    end
    else
    begin
        pwm1 = 1'b0;
        pwm2 = 1'b1;
        pwm3 = 1'b0;
        pwm4 = out;
    end
end



endmodule