pwm_t.v

来自「自己写的一个pwm模块」· Verilog 代码 · 共 21 行

`timescale 1ns/1ns
`include "PWM.v"
module PWM_t;
    reg  clk,wr_n=1,reset=1;
    reg[1:0] addr=2'b11;
    reg[15:0] wrdata=16'h0001;
    wire pwm1,pwm2,pwm3,pwm4;
 
 
    initial
        begin
            clk=0;


    
        end
        PWM    p(clk,addr,wr_n,wrdata,reset,pwm1,pwm2,pwm3,pwm4);
    always
    #1 clk=~clk; 
      
endmodule