pwm.v

自己写的一个pwm模块

module PWM(clk,addr,wr_n,wrdata,reset,pwm1,pwm2,pwm3,pwm4);
input clk,wr_n,reset; 
                      
input [1:0]addr; 
input [15:0]wrdata;  
output pwm1,pwm2,pwm3,pwm4; 
                         
 /*                      
reg [15:0]duty; 
reg [15:0]period; 
reg [15:0]counter; 
*/
//test
reg[15:0] counter=16'h0000,duty=16'h0003,period=16'h0007;
//test
reg start=1;
reg out;
reg direct=0;
reg pwm1,pwm2,pwm3,pwm4;

//test
initial
begin
    #20 direct=1;
    #18 direct=0;

#4 start=1;
end
//test


always @(posedge clk or negedge reset)
begin
    if (reset == 1'b0)
    begin
     			duty[15:0] <= 16'h0007;
			{direct,start} <= 2'b00;
			period[15:0] <= 16'h000f;
    end 
    else
    begin  
       if (wr_n == 1'b0)
       begin
           
          if (addr[1:0] == 2'b00) 
		    begin
			   {direct,start} <= wrdata[1:0];
			   period[15:0] <= period[15:0];
			   duty[15:0] <= duty[15:0];
		    end

          else if (addr[1:0] == 2'b01) 
		    begin
			   start <= start;
			   direct <= direct;
			   period[15:0] <= wrdata[15:0];
			   duty[15:0] <= duty[15:0];
		    end
		    
          else if (addr[1:0] == 2'b10) 
		    begin
			   duty[15:0] <= wrdata[15:0];
			   start <= start;
			   direct <= direct;
			   period[15:0] <= period[15:0];
		    end
		    
		    else
		    begin
			   duty[15:0] <= duty[15:0];
			   start <= start;
			   direct <= direct;
			   period[15:0] <= period[15:0];
		    end	
    
       end
	    else
	    begin
		   duty[15:0] <= duty[15:0];
		   start <= start;
		   direct <= direct;
		   period[15:0] <= period[15:0];
	    end
   end   
end

always @(posedge clk)
begin
    
    if ((wr_n == 1'b0) && (addr[1:0] == 2'b11)) 
    begin
       counter[15:0] <= wrdata[15:0];
    end
    else if (start == 1'b1)
    begin
        if (counter[15:0] < period[15:0]) counter[15:0] <= counter[15:0] + 16'b1;
        else counter[15:0] <= 16'b0;
    end
    else counter[15:0] <= counter[15:0];
    
    if (start == 1'b1)
    begin
       if (counter[15:0] <= duty[15:0]) out <= 1'b1;
       else out <= 1'b0;
   end
   else out <= 1'b0;
end

always @(out or start or direct)
begin
    if (start == 1'b0)
    begin
        pwm1 = 1'b0;
        pwm2 = 1'b0;
        pwm3 = 1'b0;
        pwm4 = 1'b0;
    end
    else if (direct == 1'b0) 
    begin
        pwm1 = 1'b1;
        pwm2 = 1'b0;
        pwm3 = out;
        pwm4 = 1'b0;
    end
    else
    begin
        pwm1 = 1'b0;
        pwm2 = 1'b1;
        pwm3 = 1'b0;
        pwm4 = out;
    end
end



endmodule