📄 modulator_map.mrp
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+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| dout<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dout<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dout<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dout<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dout<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dout<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dout<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dout<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dout<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dout<9> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dout<10> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dout<11> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dout<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dout<13> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dout<14> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dout<15> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dout<16> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || dout<17> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || ex_bds | IOB | INPUT | LVCMOS25 | | | | | || ex_clk | IOB | INPUT | LVCMOS25 | | | | | || ex_opt | IOB | INPUT | LVCMOS25 | | | | | || ex_opt0 | IOB | INPUT | LVCMOS25 | | | | | || ex_opt1 | IOB | INPUT | LVCMOS25 | | | | | || ex_pm | IOB | INPUT | LVCMOS25 | | | | | || ex_pms | IOB | INPUT | LVCMOS25 | | | | | || ex_ppt | IOB | INPUT | LVCMOS25 | | | | | || gclk | IOB | INPUT | LVCMOS25 | | | | | || io_reset | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || io_update | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || ncs | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || osk | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pdclk | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || profile<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || profile<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || profile<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || pwr_dwn | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || rt | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || sclk | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || sdio | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || sdo | IOB | INPUT | LVCMOS25 | | | | | || tp<0> | IOB | INPUT | LVCMOS25 | | | | | || tp<1> | IOB | INPUT | LVCMOS25 | | | | | || tp<2> | IOB | INPUT | LVCMOS25 | | | | | || tp<3> | IOB | INPUT | LVCMOS25 | | | | | || tp<4> | IOB | INPUT | LVCMOS25 | | | | | || tp<5> | IOB | INPUT | LVCMOS25 | | | | | || tp<6> | IOB | INPUT | LVCMOS25 | | | | | || tp<7> | IOB | INPUT | LVCMOS25 | | | | | || tp_out<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || tp_out<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || tp_out<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || tp_out<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || tp_out<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || tp_out<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | OFF1 | | || tx_en | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details--------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 55Number of Equivalent Gates for Design = 8,303Number of RPM Macros = 0Number of Hard Macros = 0DCIRESETs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DCMs = 1GCLKs = 1ICAPs = 018X18 Multipliers = 0Block RAMs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 17IOB Dual-Rate Flops not driven by LUTs = 0IOB Dual-Rate Flops = 0IOB Slave Pads = 0IOB Master Pads = 0IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 0IOB Flip Flops = 1Unbonded IOBs = 0Bonded IOBs = 55XORs = 0CARRY_INITs = 0CARRY_SKIPs = 0CARRY_MUXes = 0Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MUXFs = 10MULT_ANDs = 04 input LUTs used as Route-Thrus = 04 input LUTs = 113Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 17Slice Flip Flops = 73SliceMs = 0SliceLs = 73Slices = 73F6 Muxes = 1F5 Muxes = 9F8 Muxes = 0F7 Muxes = 0Number of LUT signals with 4 loads = 2Number of LUT signals with 3 loads = 7Number of LUT signals with 2 loads = 4Number of LUT signals with 1 load = 94NGM Average fanout of LUT = 1.61NGM Maximum fanout of LUT = 13NGM Average fanin for LUT = 3.5575Number of LUT symbols = 113⌨️ 快捷键说明
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