modulator_map.mrp

运用FPGA控制AD9957的操作

Release 8.1.03i Map I.27
Xilinx Mapping Report File for Design 'modulator'

Design Information
------------------
Command Line   : D:\Xilinx\bin\nt\map.exe -ise
E:/work/modulator_single/modulator.ise -intstyle ise -p xc3s200-ft256-4 -cm area
-pr b -k 4 -c 100 -o modulator_map.ncd modulator.ngd modulator.pcf 
Target Device  : xc3s200
Target Package : ft256
Target Speed   : -4
Mapper Version : spartan3 -- $Revision: 1.34 $
Mapped Date    : Wed Jan 30 20:21:36 2008

Design Summary
--------------
Number of errors:      0
Number of warnings:   19
Logic Utilization:
  Number of Slice Flip Flops:          73 out of   3,840    1%
  Number of 4 input LUTs:             113 out of   3,840    2%
Logic Distribution:
  Number of occupied Slices:                           73 out of   1,920    3%
    Number of Slices containing only related logic:      73 out of      73  100%
    Number of Slices containing unrelated logic:          0 out of      73    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:         113 out of   3,840    2%
  Number of bonded IOBs:               55 out of     173   31%
    IOB Flip Flops:                     1
  Number of GCLKs:                     1 out of       8   12%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  8,303
Additional JTAG gate count for IOBs:  2,640
Peak Memory Usage:  132 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network ex_pm_IBUF has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 16
   more times for the following (max. 5 shown):
   ex_bds_IBUF,
   ex_opt_IBUF,
   ex_pms_IBUF,
   ex_ppt_IBUF,
   ex_opt0_IBUF
   To see the details of these warning messages, please use the -detail switch.
WARNING:PhysDesignRules:367 - The signal <ex_opt0_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ex_opt1_IBUF> is incomplete. The
   signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <tp<0>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <tp<1>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <tp<2>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <tp<3>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <tp<4>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ex_pms_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <tp<5>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ex_opt_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <tp<6>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <tp<7>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ex_ppt_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ex_bds_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ex_pm_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <sdo_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <ex_clk_IBUF> is incomplete. The signal
   does not drive any load pins in the design.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFG symbol "clkdcm_inst/CLK0_BUFG_INST" (output signal=clk)
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------