📄 modulator.twr
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Release 8.1.03i Trace I.27
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
D:\Xilinx\bin\nt\trce.exe -ise modulator.ise -intstyle ise -e 3 -l 3 -s 4 -xml
modulator modulator.ncd -o modulator.twr modulator.pcf
Design file: modulator.ncd
Physical constraint file: modulator.pcf
Device,speed: xc3s200,-4 (PRODUCTION 1.37 2005-11-04)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock gclk to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
io_update | 11.105(R)|clk | 0.000|
ncs | 9.457(R)|clk | 0.000|
sclk | 8.867(R)|clk | 0.000|
sdio | 9.243(R)|clk | 0.000|
tp_out<0> | 7.110(R)|clk | 0.000|
tp_out<1> | 8.153(R)|clk | 0.000|
tp_out<2> | 8.177(R)|clk | 0.000|
tp_out<3> | 7.858(R)|clk | 0.000|
tp_out<5> | 6.009(R)|clk | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock gclk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
gclk | 5.965| | | |
---------------+---------+---------+---------+---------+
Analysis completed Wed Jan 30 20:22:14 2008
--------------------------------------------------------------------------------
Peak Memory Usage: 103 MB
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