modulator_sim_v.ndo

运用FPGA控制AD9957的操作

## NOTE: Do not edit this file.
## Auto generated by Project Navigator for Post-Translate Simulation
##
vlib work
## Compile Post-Translate Model
vlog  "E:/work/modulator_single/netgen/translate/modulator_translate.v"
vlog  "modulator_sim.v"
vlog  "D:/Xilinx/verilog/src/glbl.v"
vsim -t 1ps +maxdelays  -L simprims_ver -lib work modulator_sim_v glbl
do {modulator_sim_v.udo}
view wave
add wave *
add wave /glbl/GSR
view structure
view signals
run 1000ns
## End