coregen.xml

运用FPGA控制AD9957的操作

<?xml version="1.0" encoding="UTF-8"?>
<RootFolder label="COREGEN" treetype="folder" language="COREGEN">
	<Folder label="VERILOG Component Instantiation" treetype="folder">
		<Template label="dcm" treetype="template">
		</Template>
		<Template label="m" treetype="template">
		</Template>
		<Template label="uopi" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
uopi YourInstanceName (
    .DATA(DATA),
    .WE(WE),
    .A(A),
    .CLK(CLK),
    .RFD(RFD),
    .RDY(RDY),
    .SINE(SINE),
    .COSINE(COSINE));

 
		</Template>
		<Template label="poip" treetype="template">
		</Template>
		<Template label="qw" treetype="template">
		</Template>
		<Template label="po" treetype="template">
		</Template>
		<Template label="ram_ctrl" treetype="template">
		</Template>
		<Template label="sram_ctrl" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
sram_ctrl YourInstanceName (
    .addr(addr),
    .clk(clk),
    .dout(dout));

 
		</Template>
	</Folder>
	<Folder label="VHDL Component Instantiation" treetype="folder">
		<Template label="dcm" treetype="template">
		</Template>
		<Template label="m" treetype="template">
		</Template>
		<Template label="uopi" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component uopi
    port (
    DATA: IN std_logic_VECTOR(27 downto 0);
    WE: IN std_logic;
    A: IN std_logic_VECTOR(4 downto 0);
    CLK: IN std_logic;
    RFD: OUT std_logic;
    RDY: OUT std_logic;
    SINE: OUT std_logic_VECTOR(5 downto 0);
    COSINE: OUT std_logic_VECTOR(5 downto 0));
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : uopi
        port map (
            DATA =&gt; DATA,
            WE =&gt; WE,
            A =&gt; A,
            CLK =&gt; CLK,
            RFD =&gt; RFD,
            RDY =&gt; RDY,
            SINE =&gt; SINE,
            COSINE =&gt; COSINE);
 
		</Template>
		<Template label="poip" treetype="template">
		</Template>
		<Template label="qw" treetype="template">
		</Template>
		<Template label="po" treetype="template">
		</Template>
		<Template label="ram_ctrl" treetype="template">
		</Template>
		<Template label="sram_ctrl" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component sram_ctrl
    port (
    addr: IN std_logic_VECTOR(7 downto 0);
    clk: IN std_logic;
    dout: OUT std_logic_VECTOR(15 downto 0));
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : sram_ctrl
        port map (
            addr =&gt; addr,
            clk =&gt; clk,
            dout =&gt; dout);
 
		</Template>
	</Folder>
</RootFolder>