serial_wr_sim.v

来自「运用FPGA控制AD9957的操作」· Verilog 代码 · 共 70 行

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   09:08:38 12/05/2007
// Design Name:   serial_wr
// Module Name:   serial_wr_sim.v
// Project Name:  modulator
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: serial_wr
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module serial_wr_sim_v;

	// Inputs
	reg clk;
	reg nrst;
	reg [7:0] addr;
	reg [7:0] data;
	reg start;

	// Outputs
	wire sdo;
	wire ncs;
	wire sclk;
	wire gend;

	// Instantiate the Unit Under Test (UUT)
	serial_wr uut (
		.clk(clk), 
		.nrst(nrst), 
		.addr(addr), 
		.data(data), 
		.start(start), 
		.sdo(sdo), 
		.ncs(ncs), 
		.sclk(sclk), 
		.gend(gend)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		nrst = 0;
		addr = 0;
		data = 0;
		start = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule