serial_wr.stx

运用FPGA控制AD9957的操作

Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "serial_wr.v" in library work
Module <serial_wr> compiled
No errors in compilation
Analysis of file <"serial_wr.prj"> succeeded.
 
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Total memory usage is 80460 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)