rcosflt_lookup_sim.v

运用FPGA控制AD9957的操作

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   11:45:56 12/05/2007
// Design Name:   rcosflt_lookup
// Module Name:   rcosflt_lookup_sim.v
// Project Name:  modulator
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: rcosflt_lookup
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module rcosflt_lookup_sim_v;

	// Inputs
	reg clk;
	reg nrst;
	reg din;

	// Outputs
	wire [15:0] dout;

	// Instantiate the Unit Under Test (UUT)
	rcosflt_lookup uut (
		.clk(clk), 
		.nrst(nrst), 
		.din(din), 
		.dout(dout)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		nrst = 0;
		din = 0;

		// Wait 100 ns for global reset to finish
		#100;
        nrst = 1;
		// Add stimulus here
		#100;
		din = 0;
		din = 1;
	end
	initial begin
		forever #5 clk =~clk;
	end
      
endmodule