serial_sim.v

运用FPGA控制AD9957的操作

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:18:43 11/13/2007
// Design Name:   serial
// Module Name:   serial_sim.v
// Project Name:  modulator
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: serial
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module serial_sim_v;

	// Inputs
	reg clk;
	reg nrst;
	reg start;
	reg [7:0] data;
	reg [7:0] addr;

	// Outputs
	wire ncs;
	wire sclk;
	wire sdo;
	wire sdio;
	wire io_update;
	wire io_reset;
	wire end_serial;
	wire dout;

	// Instantiate the Unit Under Test (UUT)
	serial uut (
		.clk(clk), 
		.nrst(nrst), 
		.start(start), 
		.addr(addr),
		.din(data), 
		.ncs(ncs), 
		.sclk(sclk), 
		.sdo(sdo), 
		.sdio(sdio), 
		.io_update(io_update), 
		.io_reset(io_reset), 
		.dout(dout),
		.end_serial(end_serial)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		nrst = 0;
		start = 0;
		addr = 8'h01; 
		data = 8'h55;

		// Wait 100 ns for global reset to finish
		#100;
        nrst = 1;
		// Add stimulus here
		#100;
        start = 1;


	end
    initial begin
		forever clk = #10 ~clk;
	end
	always@(posedge clk)
	begin
	
	end
endmodule