modulator.syr

运用FPGA控制AD9957的操作

    -----------------------------------------------------------------------
    | States             | 12                                             |
    | Transitions        | 21                                             |
    | Inputs             | 6                                              |
    | Outputs            | 12                                             |
    | Clock              | clk (rising_edge)                              |
    | Reset              | nrst (negative)                                |
    | Reset type         | asynchronous                                   |
    | Reset State        | 0000000000000000111001100110000                |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <ncs>.
    Found 1-bit register for signal <sd_io>.
    Found 1-bit register for signal <end_serial>.
    Found 1-bit register for signal <ser_out>.
    Found 1-bit register for signal <sclk>.
    Found 64-bit register for signal <dout>.
    Found 1-bit 64-to-1 multiplexer for signal <$n0000> created at line 191.
    Found 8-bit subtractor for signal <$n0089> created at line 183.
    Found 2-bit adder for signal <$n0092>.
    Found 2-bit register for signal <dly_cnt>.
    Found 1-bit register for signal <g_addr_data>.
    Found 8-bit register for signal <shift_cnt>.
    Found 64-bit register for signal <shift_data>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred 136 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   1 Multiplexer(s).
Unit <serial> synthesized.


Synthesizing Unit <ad9957_single>.
    Related source file is "ad9957_single.v".
WARNING:Xst:1305 - Output <io_reset> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <sdo> is never used.
WARNING:Xst:646 - Signal <sgl_dly_cnt> is assigned but never used.
WARNING:Xst:1780 - Signal <ad9957_ram> is never used or assigned.
WARNING:Xst:1780 - Signal <ad9957_saf> is never used or assigned.
WARNING:Xst:1780 - Signal <ad9957_gpio_data> is never used or assigned.
WARNING:Xst:646 - Signal <data_out> is assigned but never used.
WARNING:Xst:1780 - Signal <ad9957_profile0> is never used or assigned.
WARNING:Xst:1780 - Signal <ad9957_profile1> is never used or assigned.
WARNING:Xst:1780 - Signal <ad9957_profile2> is never used or assigned.
WARNING:Xst:1780 - Signal <ad9957_profile3> is never used or assigned.
WARNING:Xst:1780 - Signal <ad9957_profile4> is never used or assigned.
WARNING:Xst:1780 - Signal <ad9957_profile5> is never used or assigned.
WARNING:Xst:1780 - Signal <ad9957_profile6> is never used or assigned.
WARNING:Xst:1780 - Signal <ad9957_profile7> is never used or assigned.
WARNING:Xst:1780 - Signal <ad9957_multichip_sync> is never used or assigned.
WARNING:Xst:1780 - Signal <ad9957_ioupdate_rate> is never used or assigned.
WARNING:Xst:1780 - Signal <ad9957_gpio_config> is never used or assigned.
WARNING:Xst:1780 - Signal <ad9957_cfr1> is never used or assigned.
WARNING:Xst:1780 - Signal <ad9957_cfr2> is never used or assigned.
WARNING:Xst:1780 - Signal <ad9957_cfr3> is never used or assigned.
WARNING:Xst:1780 - Signal <ad9957_ram_seg0> is never used or assigned.
WARNING:Xst:1780 - Signal <ad9957_ram_seg1> is never used or assigned.
WARNING:Xst:1780 - Signal <ad9957_aux_dac> is never used or assigned.
    Register <io_update> equivalent to <end_single> has been removed
    Found finite state machine <FSM_1> for signal <state_cur>.
    -----------------------------------------------------------------------
    | States             | 14                                             |
    | Transitions        | 21                                             |
    | Inputs             | 3                                              |
    | Outputs            | 14                                             |
    | Clock              | clk (rising_edge)                              |
    | Reset              | $n0000 (negative)                              |
    | Reset type         | synchronous                                    |
    | Reset State        | 000000000000000000000000000000000000000000000000001101001011001000110110001100101       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit tristate buffer for signal <sdio>.
    Found 1-bit register for signal <end_single>.
    Found 64-bit register for signal <data_in>.
    Found 7-bit register for signal <len_reg>.
    Found 8-bit register for signal <ser_addr>.
    Found 1-bit register for signal <ser_in>.
    Found 1-bit register for signal <ser_start>.
    Found 3-bit register for signal <ser_start_sync>.
    Found 3-bit register for signal <start_sync>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  88 D-type flip-flop(s).
	inferred   1 Tristate(s).
Unit <ad9957_single> synthesized.


Synthesizing Unit <dcmclk>.
    Related source file is "dcmclk.v".
Unit <dcmclk> synthesized.


Synthesizing Unit <modulator>.
    Related source file is "modulator.v".
WARNING:Xst:647 - Input <ex_pm> is never used.
WARNING:Xst:647 - Input <ex_bds> is never used.
WARNING:Xst:647 - Input <ex_opt> is never used.
WARNING:Xst:647 - Input <ex_pms> is never used.
WARNING:Xst:647 - Input <tp> is never used.
WARNING:Xst:647 - Input <ex_ppt> is never used.
WARNING:Xst:647 - Input <ex_opt1> is never used.
WARNING:Xst:647 - Input <ex_clk> is never used.
WARNING:Xst:646 - Signal <ex_opt0_sync<2>> is assigned but never used.
WARNING:Xst:646 - Signal <start_qudc> is assigned but never used.
WARNING:Xst:646 - Signal <start_dac> is assigned but never used.
INFO:Xst:1533 - Unexpected state value "100000000" found while examining if signal <state_cur> describes a FSM.
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <state_cur> of Case statement line 174 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
   	- add an 'INIT' attribute on signal <state_cur> (optimization is then done without any risk)
   	- use the attribute 'signal_encoding user' to avoid onehot optimization
   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Using one-hot encoding for signal <state_cur>.
    Found 1-bit register for signal <tp_out<5>>.
    Found 4-bit register for signal <tp_out<3:0>>.
    Found 4-bit adder for signal <$n0000> created at line 142.
    Found 3-bit register for signal <ex_opt0_sync>.
    Found 1-bit register for signal <start_single>.
    Found 9-bit register for signal <state_cur>.
    Summary:
	inferred   9 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <modulator> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 3
 2-bit adder                                           : 1
 4-bit adder                                           : 1
 8-bit subtractor                                      : 1
# Registers                                            : 89
 1-bit register                                        : 79
 2-bit register                                        : 1
 3-bit register                                        : 3
 64-bit register                                       : 2
 7-bit register                                        : 1
 8-bit register                                        : 2
 9-bit register                                        : 1
# Multiplexers                                         : 1
 1-bit 64-to-1 multiplexer                             : 1
# Tristates                                            : 1
 1-bit tristate buffer                                 : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <ad9957_single_inst/state_cur> on signal <state_cur[1:4]> with sequential encoding.
-----------------------------------------------------------------------------------------------
 State                                                                             | Encoding
-----------------------------------------------------------------------------------------------
 000000000000000000000000000000000000000000000000000000000011001010110111001100100 | 1101
 000000000000000000000000000000000000000000000000001100101011011100110010000110000 | 0100
 000000000000000000000000000000000000000000000000001100101011011100110010000110001 | 1000
 000000000000000000000000000000000000000000000000001100101011011100110010000110010 | 1100
 000000000000000000000000000000000000000000000000001101001011001000110110001100101 | 0000
 000000000000000000000000000000000000000000000000001110000011100100110010100110000 | 0001
 000000000000000000000000000000000000000000000000001110000011100100110010100110001 | 0101
 000000000000000000000000000000000000000000000000001110000011100100110010100110010 | 1001
 000000000000000000000000000000000000000000111011101100001011010010111010000110000 | 0011
 000000000000000000000000000000000000000000111011101100001011010010111010000110001 | 0111
 000000000000000000000000000000000000000000111011101100001011010010111010000110010 | 1011
 000000000000000000000000000000000011100110111010001100001011100100111010000110000 | 0010
 000000000000000000000000000000000011100110111010001100001011100100111010000110001 | 0110
 000000000000000000000000000000000011100110111010001100001011100100111010000110010 | 1010
-----------------------------------------------------------------------------------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <ad9957_single_inst/serl/state_cur> on signal <state_cur[1:4]> with sequential encoding.
---------------------------------------------
 State                           | Encoding
---------------------------------------------
 0000000000000000111001100110000 | 0000
 0000000000000000111001100110001 | 0001
 0000000000000000111001100110010 | 0010
 0000000000000000111001100110011 | 0011
 0000000000000000111001100110100 | 0100
 0000000000000000111001100110101 | 0101
 0000000000000000111001100110110 | 0110
 0000000000000000111001100110111 | 1000
 0000000000000000111001100111000 | 1001
 0000000000000000111001100111001 | 1010
 0000000011001010110111001100100 | 0111
 0000000011100110011000100110000 | 1011
---------------------------------------------

Synthesizing (advanced) Unit <ad9957_single>.
INFO:Xst:2387 - HDL ADVISOR - A 3-bit shift register was found for signal <start_sync<2>> and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
INFO:Xst:2387 - HDL ADVISOR - A 3-bit shift register was found for signal <ser_start_sync<2>> and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
Unit <ad9957_single> synthesized (advanced).
WARNING:Xst:1710 - FF/Latch  <data_in_35> (without init value) has a constant value of 0 in block <ad9957_single>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_in_36> (without init value) has a constant value of 0 in block <ad9957_single>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_in_37> (without init value) has a constant value of 0 in block <ad9957_single>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_in_38> (without init value) has a constant value of 0 in block <ad9957_single>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_in_39> (without init value) has a constant value of 0 in block <ad9957_single>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_in_40> (without init value) has a constant value of 0 in block <ad9957_single>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_in_41> (without init value) has a constant value of 0 in block <ad9957_single>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_in_42> (without init value) has a constant value of 0 in block <ad9957_single>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_in_43> (without init value) has a constant value of 0 in block <ad9957_single>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_in_44> (without init value) has a constant value of 0 in block <ad9957_single>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_in_45> (without init value) has a constant value of 0 in block <ad9957_single>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_in_46> (without init value) has a constant value of 0 in block <ad9957_single>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_in_47> (without init value) has a constant value of 0 in block <ad9957_single>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_in_48> (without init value) has a constant value of 0 in block <ad9957_single>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_in_49> (without init value) has a constant value of 0 in block <ad9957_single>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <data_in_50> (without init value) has a constant value of 0 in block <ad9957_single>.