modulator.syr

运用FPGA控制AD9957的操作

Release 8.1.03i - xst I.27
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.92 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
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--> Reading design: modulator.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "modulator.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "modulator"
Output Format                      : NGC
Target Device                      : xc3s200-4-ft256

---- Source Options
Top Module Name                    : modulator
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : modulator.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "serial.v" in library work
Compiling verilog file "dcmclk.v" in library work
Module <serial> compiled
Compiling verilog file "ad9957_single.v" in library work
Module <dcmclk> compiled
Compiling verilog file "modulator.v" in library work
Module <ad9957_single> compiled
Module <modulator> compiled
No errors in compilation
Analysis of file <"modulator.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
WARNING:HDLCompilers:261 - "ad9957_single.v" line 387 Connection to output port 'dout' does not match port size
Analyzing top module <modulator>.
	IDLE = "idle"
	START = "start"
	SINGLE_START = "s_str"
	SINGLE_END = "s_end"
	DAC_START = "d_str"
	DAC_END = "d_end"
	QUDC_START = "q_str"
	QUDC_END = "q_end"
	END = "end"
Module <modulator> is correct for synthesis.
 
Analyzing module <dcmclk>.
Module <dcmclk> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <dcmclk>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <dcmclk>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <dcmclk>.
    Set user-defined property "CLKDV_DIVIDE =  2.0000000000000000" for instance <DCM_INST> in unit <dcmclk>.
    Set user-defined property "CLKFX_DIVIDE =  1" for instance <DCM_INST> in unit <dcmclk>.
    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <DCM_INST> in unit <dcmclk>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <dcmclk>.
    Set user-defined property "CLKIN_PERIOD =  10.0000000000000000" for instance <DCM_INST> in unit <dcmclk>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <dcmclk>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <dcmclk>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <dcmclk>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <dcmclk>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <dcmclk>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <dcmclk>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <dcmclk>.
    Set user-defined property "FACTORY_JF =  8080" for instance <DCM_INST> in unit <dcmclk>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <dcmclk>.
    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <DCM_INST> in unit <dcmclk>.
Analyzing module <ad9957_single>.
	CFR1 = 8'b00000000
	CFR2 = 8'b00000001
	CFR3 = 8'b00000010
	AUX_DAC = 8'b00000011
	IO_UP_RATE = 8'b00000100
	RAM_SEG0 = 8'b00000101
	RAM_SEG1 = 8'b00000110
	SAF = 8'b00001001
	MUL_SYNC = 8'b00001010
	PRF0 = 8'b00001110
	PRF1 = 8'b00001111
	PRF2 = 8'b00010000
	PRF3 = 8'b00010001
	PRF4 = 8'b00010010
	PRF5 = 8'b00010011
	PRF6 = 8'b00010100
	PRF7 = 8'b00010101
	LEN32 = 32'sb00000000000000000000000000100000
	LEN64 = 32'sb00000000000000000000000001000000
	IDLE = "idle"
	SER0_PRE = "pre0"
	SER0_START = "start0"
	SER0_WAIT = "wait0"
	SER0_END = "end0"
	SER1_PRE = "pre1"
	SER1_START = "start1"
	SER1_WAIT = "wait1"
	SER1_END = "end1"
	SER2_PRE = "pre2"
	SER2_START = "start2"
	SER2_WAIT = "wait2"
	SER2_END = "end2"
	SIG_END = "end"
	Enabling task <init>.
	Enabling task <init>.
	Enabling task <init>.
Module <ad9957_single> is correct for synthesis.
 
Analyzing module <serial>.
	STATE_IDLE = "s0"
	STATE1 = "s1"
	STATE2 = "s2"
	STATE3 = "s3"
	STATE4 = "s4"
	STATE5 = "s5"
	STATE6 = "s6"
	STATE7 = "s7"
	STATE8 = "s8"
	STATE9 = "s9"
	STATE10 = "s10"
	STATE11 = "end"
	Enabling task <init>.
	Enabling task <init>.
INFO:Xst:1433 - Contents of array <shift_data> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
Module <serial> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <profile> in unit <ad9957_single> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sgl_dly_cnt> in unit <ad9957_single> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <serial>.
    Related source file is "serial.v".
    Found finite state machine <FSM_0> for signal <state_cur>.