serial_wr.v

来自「运用FPGA控制AD9957的操作」· Verilog 代码 · 共 198 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:28:51 11/30/2007 
// Design Name: 
// Module Name:    serial_wr 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module serial_wr(clk, nrst, addr, data, start, sdio, ncs, sclk, gend);
    input clk;
    input nrst;
    input [7:0] addr;
    input [7:0] data;
    input start;
    output sdio;
    output ncs;
    output sclk;
    output gend;
	//////////////////////////////////////////////////////////////////////////
	reg sdio;
    reg ncs;
    reg sclk;
    reg gend;
	//////////////////////////////////////////////////////////////////////////
	reg g_addr_data;
	reg [7:0] shift_data,shift_cnt;
	reg [4:0] state_cur,state_next;
	parameter 	STATE_IDLE = 5'b00000,
				STATE1 = 5'b0001,
				STATE2 = 5'b0010,
				STATE3 = 5'b0011,
				STATE4 = 5'b0111,
				STATE5 = 5'b0110,
				STATE6 = 5'b0100,
				STATE7 = 5'b0101,
				STATE8 = 5'b1101,
				STATE9 = 5'b1101;
	parameter LEN_WORD = 8;
	reg[1:0] dly_cnt;
	//////////////////////////////////////////////////////////////////////////
	//wr
	always@(posedge clk,negedge nrst)
	begin
		if(!nrst)
			state_cur <= STATE_IDLE;
		else
			state_cur <= state_next;
	end
	////////////////////////////////
	//
	always@(nrst,state_cur,shift_cnt,start,dly_cnt)
	begin
		if(!nrst)
			state_next <= STATE_IDLE;
		else
		begin
			case(state_cur)
				STATE_IDLE:
				begin
					if(start == 1)
						state_next <= STATE1;
					else
						state_next <= STATE_IDLE;
				end
				/////////////////////////write addr/data to serial interface
				STATE1:
				begin
						state_next <= STATE2;
				end
				STATE2:							//delay 4 clk period
				begin
					if(dly_cnt == 3)
						state_next <= STATE3;
				end
				STATE3:                      	//delay 4 clk period
				begin
					if(dly_cnt == 3)
						state_next <= STATE4;
				end
				STATE4:
				begin
					if(shift_cnt == 0)			// end to write 
						state_next <= STATE5;
					else						// continue to write
						state_next <= STATE1;
				end
				STATE5:
				begin
					if(g_addr_data == 0)      	//start to write/read data
						state_next <= STATE6;
					else						//end to write data
						state_next <= STATE7;
				end
				STATE6:
				begin
					state_next <= STATE1;
				end
				/////////////////////////end
				STATE7:
				begin
					if(start != 0)				//wait for end signal 
						state_next <= STATE7;
					else                    
						state_next <= STATE_IDLE;
				end
				default:
				begin
					state_next <= STATE_IDLE;
				end
			endcase
		end
	end
	//////////////////////////////////
	always@(posedge clk)
	begin
		if(!nrst)
			init;		
		else
		begin
			case(state_cur)
				STATE_IDLE:
				begin
					init;
				end
				STATE1:
				begin
					ncs <= 1'b0;
					sdio <= shift_data[shift_cnt];
					sclk <= 1'b0;
				end
				STATE2:
				begin
					if(dly_cnt == 3)
						dly_cnt <= 0;
					else
						dly_cnt <= dly_cnt + 1;
				end
				STATE3:
				begin
					sclk <= 1'b1;
					if(dly_cnt == 3)
						dly_cnt <= 0;
					else
						dly_cnt <= dly_cnt + 1;
				end
				STATE4:
				begin
					sclk <= 1'b1;
					if(shift_cnt != 0)
						shift_cnt <= shift_cnt - 1;
				end
				STATE5:
				begin
					shift_cnt <= 3'b111;
				end
				STATE6:
				begin
					g_addr_data <= 1'b1;
					ncs <= 1'b1;
				end
				/////////////////////////read data from serial interface
				STATE7:
				begin
					gend <= 1'b1;
				end
				default:
				begin
				end
			endcase
		end
	end
	/////////////////////////////////////////
	/////////////////////////////////////////
	task init;
	begin
		ncs <= 1'b1;
		sdio <= 1'b0;
		sclk <= 1'b0;
		gend <= 1'b0;
		shift_data <= addr;
		shift_cnt <= LEN_WORD - 1;
		g_addr_data <= 1'b0;
	end
	endtask
endmodule