📄 modulator.drc

📁 运用FPGA控制AD9957的操作
💻 DRC
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WARNING:PhysDesignRules:367 - The signal <ex_opt0_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <ex_opt1_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <tp<0>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <tp<1>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <tp<2>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <tp<3>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <tp<4>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <ex_pms_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <tp<5>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <ex_opt_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <tp<6>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <tp<7>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <ex_ppt_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <ex_bds_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <ex_pm_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <sdo_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <ex_clk_IBUF> is incomplete. The signal
   does not drive any load pins in the design.DRC detected 0 errors and 17 warnings.
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