modulator.drc

来自「运用FPGA控制AD9957的操作」· DRC 代码 · 共 36 行

DRC
36 行
字号 
WARNING:PhysDesignRules:367 - The signal <ex_opt0_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <ex_opt1_IBUF> is incomplete. The
   signal does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <tp<0>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <tp<1>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <tp<2>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <tp<3>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <tp<4>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <ex_pms_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <tp<5>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <ex_opt_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <tp<6>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <tp<7>_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <ex_ppt_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <ex_bds_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <ex_pm_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <sdo_IBUF> is incomplete. The signal
   does not drive any load pins in the design.WARNING:PhysDesignRules:367 - The signal <ex_clk_IBUF> is incomplete. The signal
   does not drive any load pins in the design.DRC detected 0 errors and 17 warnings.

modulator.drc - 源码说明

本页面展示了「运用FPGA控制AD9957的操作」中的 modulator.drc 源码文件，采用 DRC 编程语言编写，共 36 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

虫虫开发者社区收录了大量与fpga相关的技术资源，包括源代码、技术文档、电路图等，是电子工程师和嵌入式开发者的专业学习平台。

⌨️ 快捷键说明

复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?