_primary.vhd

来自「运用FPGA控制AD9957的操作」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity dcmclk is
    port(
        CLKIN_IN        : in     vl_logic;
        CLKIN_IBUFG_OUT : out    vl_logic;
        CLK0_OUT        : out    vl_logic;
        LOCKED_OUT      : out    vl_logic
    );
end dcmclk;