modulator_sim.v

运用FPGA控制AD9957的操作

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:40:53 12/07/2007
// Design Name:   modulator
// Module Name:   modulator_sim.v
// Project Name:  modulator
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: modulator
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module modulator_sim_v;

	// Inputs
	reg gclk;
//	reg nrst;
	reg ex_opt;
	reg ex_opt0;
	reg ex_opt1;
	reg ex_ppt;
	reg ex_pm;
	reg ex_pms;
	reg ex_bds;
	reg ex_clk;
	reg sdo;
	reg [7:0] tp;

	// Outputs
	wire [17:0] dout;
	wire io_update;
	wire io_reset;
	wire osk;
	wire tx_en;
	wire pdclk;
	wire rt;
	wire pwr_dwn;
	wire [2:0] profile;
	wire sdio;
	wire ncs;
	wire sclk;
	wire [5:0] tp_out;

	// Instantiate the Unit Under Test (UUT)
	modulator uut (
		.gclk(gclk), 
//		.nrst(nrst), 
		.ex_opt(ex_opt), 
		.ex_opt0(ex_opt0), 
		.ex_opt1(ex_opt1), 
		.ex_ppt(ex_ppt), 
		.ex_pm(ex_pm), 
		.ex_pms(ex_pms), 
		.ex_bds(ex_bds), 
		.ex_clk(ex_clk), 
		.dout(dout), 
		.io_update(io_update), 
		.io_reset(io_reset), 
		.osk(osk), 
		.tx_en(tx_en), 
		.pdclk(pdclk), 
		.rt(rt), 
		.pwr_dwn(pwr_dwn), 
		.profile(profile), 
		.sdio(sdio), 
		.sdo(sdo), 
		.ncs(ncs), 
		.sclk(sclk), 
		.tp(tp), 
		.tp_out(tp_out)
	);

	initial begin
		// Initialize Inputs
		gclk = 0;
//		nrst = 0;
		ex_opt = 0;
		ex_opt0 = 0;
		ex_opt1 = 0;
		ex_ppt = 0;
		ex_pm = 0;
		ex_pms = 0;
		ex_bds = 0;
		ex_clk = 0;
		sdo = 0;
		tp = 0;

		// Wait 100 ns for global reset to finish
		#100;
 //       nrst = 1;
		ex_opt0 = 1;
		#100;
		ex_opt0 = 0;
		// Add stimulus here
		
	end
	initial begin
		forever #5 gclk = ~gclk;
		
	end
      
endmodule