ad9957_single.v

运用FPGA控制AD9957的操作

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:15:53 12/05/2007 
// Design Name: 
// Module Name:    ad9957_single 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ad9957_single(clk, nrst, start, ncs, sclk, sdio, sdo, io_update, io_reset, profile,end_single);
    input clk;
    input nrst;
    input start;
	input sdo;
    
	output ncs;
    output sclk;
    output sdio;
    output io_update;
    output io_reset;
    output [2:0] profile;
	output end_single;

	////////////////////////////////////////////////////////////////////////////////
//	reg ncs;
//    reg sclk;
//    reg sdio;
     reg io_update;
//    reg io_reset;
    reg [2:0] profile;
	reg end_single;
//	assign io_reset = 0;
//	assign io_update = 0;
	//////////////////////////////////////////////////////////////////////////////////
	////AD9957 REGTISTER
	reg[31:0] ad9957_cfr1;				//8'h00
	reg[31:0] ad9957_cfr2;				//8'h01
	reg[31:0] ad9957_cfr3;				//8'h02
	reg[31:0] ad9957_aux_dac;			//8'h03
	reg[31:0] ad9957_ioupdate_rate;		//8'h04
	reg[47:0] ad9957_ram_seg0;			//8'h05
	reg[47:0] ad9957_ram_seg1;			//8'h06
	reg[31:0] ad9957_saf;				//8'h09
	reg[31:0] ad9957_multichip_sync;	//8'h0a
	reg[63:0] ad9957_profile0;			//8'h0e
	reg[63:0] ad9957_profile1;			//8'h0f
	reg[63:0] ad9957_profile2;			//8'h10
	reg[63:0] ad9957_profile3;			//8'h11
	reg[63:0] ad9957_profile4;			//8'h12
	reg[63:0] ad9957_profile5;			//8'h13
	reg[63:0] ad9957_profile6;			//8'h14
	reg[63:0] ad9957_profile7;			//8'h15
	reg[31:0] ad9957_ram;				//8'h16
	reg[15:0] ad9957_gpio_config;		//8'h18
	reg[15:0] ad9957_gpio_data;			//8'h19
	//REG parameter write
	parameter CFR1 = 8'h00;
	parameter CFR2 = 8'h01;
	parameter CFR3 = 8'h02;
	parameter AUX_DAC = 8'h03;
	parameter IO_UP_RATE = 8'h04;
	parameter RAM_SEG0 = 8'h05;
	parameter RAM_SEG1 = 8'h06;
	parameter SAF = 8'h09;
	parameter MUL_SYNC = 8'h0a;
	parameter PRF0 = 8'h0e; 
	parameter PRF1 = 8'h0f;
	parameter PRF2 = 8'h10;
	parameter PRF3 = 8'h11;
	parameter PRF4 = 8'h12;
	parameter PRF5 = 8'h13;
	parameter PRF6 = 8'h14;
	parameter PRF7 = 8'h15;
	parameter LEN32 = 32;
	parameter LEN64 = 64;
	
	//////////////////////////////////////////////////////////////////////////////////
	// parameter setting
//	parameter IDLE = "IDLE";
//	parameter CFG1 = "cfr1";
//	parameter CFG2 = "cfr2";
//	parameter CFG3 = "cfr3";
//	parameter AUX_DAC = "aux_dac";
//	parameter IO_RATE = "ioupdate_rate";
//	parameter SAF = "saf";
//	parameter PRF0 = "profile0";
//	parameter PRF1 = "profile1";
//	parameter PRF2 = "profile2";
//	parameter PRF3 = "profile3";
//	parameter PRF4 = "profile4";
//	parameter PRF5 = "profile5";
//	parameter PRF6 = "profile6";
//	parameter PRF7 = "profile7";
//	parameter GPIO_C = "gpio_cfg";
//	parameter GPIO_D = "gpio_dat";
//	parameter END = "end";
//	parameter DLY_CFG1 = "dly_0";
//	parameter DLY_CFG2 = "dly_1";
//	parameter DLY_CFG3 = "dly_2";
//	parameter DLY_AUX_DAC = "dly_3";
//	parameter DLY_IO_RATE = "dly_4";
//	parameter DLY_SAF = "dly_5";
//	parameter DLY_PRF0 = "dly_6";
	//////////////////////////////////////////////////////////////////////////////////
	//
	reg [63:0] data_in;
	reg [7:0] ser_addr;
	wire ser_end;
	reg ser_start;
	reg [2:0] sgl_dly_cnt;
	//////////////////////////////////////////////////////////////////////////////////
	//single tone mode 
	//valiable
	reg [6:0] len_reg; 
	reg[80:0] state_cur,state_nxt;
	//parameter setting
	parameter IDLE = "idle";
	parameter SER0_PRE = "pre0";
	parameter SER0_START = "start0";
	parameter SER0_WAIT = "wait0";
	parameter SER0_END = "end0";
	parameter SER1_PRE = "pre1";
	parameter SER1_START = "start1";
	parameter SER1_WAIT = "wait1";
	parameter SER1_END = "end1";
	parameter SER2_PRE = "pre2";
	parameter SER2_START = "start2";
	parameter SER2_WAIT = "wait2";
	parameter SER2_END = "end2";
	parameter SIG_END = "end";
	//sync
	reg [2:0] start_sync,ser_start_sync;
	always@(posedge clk)
	begin
		if(!nrst)
			start_sync <= 3'b000;
		else
			start_sync <= {start_sync[1:0],start};
	end
	always@(posedge clk)
	begin
		if(!nrst)
			ser_start_sync <= 3'b000;
		else
			ser_start_sync <= {ser_start_sync[1:0],ser_start};
	end
	//fsm1
	always@(posedge clk)
	begin
		if(!nrst)
			state_cur <= IDLE;
		else
			state_cur <= state_nxt; 
	end
	//fsm2
	always@*//(nrst,state_cur,start,ser_end,sgl_dly_cnt)
	begin
		if(!nrst)
		begin
			state_nxt <= IDLE;
		end
		else
		begin
			case(state_cur)
				IDLE:
				begin
					if(start_sync[2] == 1)
						state_nxt <= SER0_PRE;
					else
						state_nxt <= IDLE;
				end
				SER0_PRE:						  		//																
				begin
					state_nxt <= SER0_START;
				end
				SER0_START:
				begin
					state_nxt <= SER0_WAIT;
				end
				SER0_WAIT:								//
				begin
					if(ser_start_sync[2] == 1'b1)
						state_nxt <= SER0_END;
					else
						state_nxt <= SER0_WAIT;
				end
				SER0_END:
				begin
					if(ser_end == 1'b1)
						state_nxt <= SER1_PRE;
					else
						state_nxt <= SER0_END;
				end
				SER1_PRE:								//
				begin
					state_nxt <= SER1_START;
				end
				SER1_START:
				begin
					state_nxt <= SER1_WAIT;
				end
				SER1_WAIT:							//AUX_DAC
				begin
					if(ser_start_sync[2] == 1'b1)
						state_nxt <= SER1_END;
					else
						state_nxt <= SER1_WAIT;
				end
				SER1_END:
				begin
					if(ser_end == 1)
						state_nxt <= SER2_PRE;
					else
						state_nxt <= SER1_END;
				end
				SER2_PRE:								//
				begin
					state_nxt <= SER2_START;
				end
				SER2_START:
				begin
					state_nxt <= SER2_WAIT;
				end
				SER2_WAIT:							//AUX_DAC
				begin
					if(ser_start_sync[2] == 1'b1)
						state_nxt <= SER2_END;
					else
						state_nxt <= SER2_WAIT;
				end
				SER2_END:
				begin
					if(ser_end == 1)
						state_nxt <= SIG_END;
					else
						state_nxt <= SER2_END;
				end
				SIG_END:
				begin
					state_nxt <= SIG_END;
				end
				default:
				begin
					state_nxt <= IDLE;
				end
			endcase
		end
	end
	//fsm3
	always@(posedge clk)
	begin
		if(!nrst)
		begin
			ser_start <= 0;
			end_single <= 1'b0;
			data_in <= 32'h0000;
			len_reg <= 7'b0000000;
			ser_addr <= 8'h00;
			init;
		end
		else
		begin
			case(state_cur)
				IDLE:
				begin
					ser_start <= 0;
					init;
				end
				SER0_PRE:						  		//																
				begin
					len_reg <= LEN32;
					ser_addr <= CFR1;
					// single mode 
					data_in <= 32'h01000000;
				end
				SER0_START:
				begin
					ser_start <= 1;
				end
				SER0_WAIT:								//
				begin
					ser_start <= 1;
				end
				SER0_END:
				begin
					ser_start <= 0;
				end
				SER1_PRE:								//
				begin
					len_reg <= LEN32;
					ser_addr <= CFR3;      				//
					//DRVO = 01;VCO_VEL=000;ICP=111;
					data_in <= 32'h40388100;
				end
				SER1_START:
				begin
					ser_start <= 1;
				end
				SER1_WAIT:							
				begin
					ser_start <= 1;
				end
				SER1_END:
				begin
					ser_start <= 0;
				end
				SER2_PRE:								//
				begin
					len_reg <= LEN64;
					ser_addr <= PRF0;      //profile0 single
					//FTW = 8'h01000000;POW = 8'h0000;ASF = 8'h0010  
					data_in <= 64'h0010000001000000;
				end
				SER2_START:
				begin
					ser_start <= 1;
				end
				SER2_WAIT:							
				begin
					ser_start <= 1;
				end
				SER2_END:
				begin
					ser_start <= 0;
				end
				SIG_END:
				begin
					end_single <= 1'b1;
					profile =3'b000;
					io_update <=1'b1;
				end
				default:
				begin
					init;
				end
			endcase
		end
	end
	//init
	task init;
	begin
		ser_start <= 0;
		end_single <= 1'b0;
		sgl_dly_cnt <= 3'b000;
		profile =3'b000;
		io_update <=1'b0;
	end
	endtask
	////////////////////////////////////////////////////////////////////////////////
	//serial interface
	reg ser_in/*synthesize syn_keep = 1*/;
	wire ser_out;
	wire sd_io;
//	assign ser_in = sdio;
//	assign tp_out = {ser_in,tst_out}; 
	always@(posedge clk)
	begin
		if(!nrst)
			ser_in <= 1'b0;
		else
			ser_in <= sdio;
	end
	assign sdio = (sd_io == 0)?ser_out:1'bz;
	serial serl(
		.clk(clk), 
		.nrst(nrst), 
		.start(ser_start),
		.len_reg(len_reg),
		.addr(ser_addr),
		.din(data_in), 
		.ncs(ncs), 
		.sclk(sclk), 
		.ser_in(ser_in), 
		.ser_out(ser_out), 
		.sd_io(sd_io),
		.dout(data_out),
		.end_serial(ser_end)
	);
endmodule