0modelsim_work.mgf

I2C总线控制器 altera公司提供VHDL实现代码

G datac_width integer = 36
G datad_width integer = 36
G dataout_width integer = 72
P dataa _in wire[35:0]
V dataa - - - -
P datab _in wire[35:0]
V datab - - - -
P datac _in wire[35:0]
V datac - - - -
P datad _in wire[35:0]
V datad - - - -
P signx _in wire
V signx - - - -
P signy _in wire
V signy - - - -
P addnsub0 _in wire
V addnsub0 - - - -
P addnsub1 _in wire
V addnsub1 - - - -
P zeroacc _in wire
V zeroacc - - - -
P dataout_global _in wire[71:0]
V dataout_global - - - -
P dataout _out wire[71:0]
V dataout - - - -
P accoverflow _out wire
V accoverflow - - - -
IB
ISB add_or_sub  reg[52:0]
ISP sign_a _in reg
ISP data_a _in reg[dataa_width-1:0]
ISP sign_b _in reg
ISP data_b _in reg[datab_width-1:0]
ISP operation _in reg
ISE add_or_sub
ISB add_or_sub_accum  reg[52:0]
ISP sign_a _in reg
ISP data_a _in reg[dataa_width+15:0]
ISP sign_b _in reg
ISP data_b _in reg[dataa_width-1:0]
ISP operation _in reg
ISE add_or_sub_accum
IE
X stratix_mac_out_internal
V 000051 12 617 1071731857826 stratix_ram_register
E stratix_ram_register VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G data_width integer = 144
G sclr string = "true"
G preset string = "false"
P data _in wire[143:0]
V data - - - -
P clk _in wire
V clk - - - -
P aclr _in wire
V aclr - - - -
P ena _in wire
V ena - - - -
P if_clk _in wire
V if_clk - - - -
P if_aclr _in wire
V if_aclr - - - -
P if_ena _in wire
V if_ena - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
P power_up _in wire
V power_up - - - -
P dataout _out wire[143:0]
V dataout - - - -
P aclrout _out wire
V aclrout - - - -
P done _out wire
V done - - - -
X stratix_ram_register
V 000048 12 157 1071731857831 stratix_ram_clear
E stratix_ram_clear VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P aclr _in wire
V aclr - - - -
P d _in wire
V d - - - -
P q _out wire
V q - - - -
X stratix_ram_clear
V 000052 12 1785 1071731857835 stratix_ram_internal
E stratix_ram_internal VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G operation_mode string = "single_port"
G ram_block_type string = "M512"
G mixed_port_feed_through_mode string = "dont_care"
G port_a_data_width integer = 16
G port_b_data_width integer = 16
G port_a_address_width integer = 16
G port_b_address_width integer = 16
G port_a_byte_enable_mask_width integer = 16
G port_b_byte_enable_mask_width integer = 16
G init_file_layout string = "none"
G port_a_first_address integer = 0
G port_a_last_address integer = 4096
G port_b_first_address integer = 0
G port_b_last_address integer = 4096
G port_a_address_clear string = "none"
G port_b_address_clear string = "none"
G mem1 integer = 512'b0
G mem2 integer = 512'b0
G mem3 integer = 512'b0
G mem4 integer = 512'b0
G mem5 integer = 512'b0
G mem6 integer = 512'b0
G mem7 integer = 512'b0
G mem8 integer = 512'b0
G mem9 integer = 512'b0
P port_a_write_enable _in wire
V port_a_write_enable - - - -
P port_b_write_enable _in wire
V port_b_write_enable - - - -
P cleara _in wire
V cleara - - - -
P clearb _in wire
V clearb - - - -
P port_a_data_in _in wire[143:0]
V port_a_data_in - - - -
P port_b_data_in _in wire[143:0]
V port_b_data_in - - - -
P port_a_address _in wire[15:0]
V port_a_address - - - -
P port_b_address _in wire[15:0]
V port_b_address - - - -
P port_a_byte_ena_mask _in wire[15:0]
V port_a_byte_ena_mask - - - -
P port_b_byte_ena_mask _in wire[15:0]
V port_b_byte_ena_mask - - - -
P port_b_read_enable _in wire
V port_b_read_enable - - - -
P port_a_clock _in wire
V port_a_clock - - - -
P port_b_clock _in wire
V port_b_clock - - - -
P same_clock _in wire
V same_clock - - - -
P port_a_data_out _out wire[143:0]
V port_a_data_out - - - -
P port_b_data_out _out wire[143:0]
V port_b_data_out - - - -
X stratix_ram_internal
V 000049 12 2921 1071731857840 stratix_ram_block
E stratix_ram_block VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G mem1 integer = 512'b0
G mem2 integer = 512'b0
G mem3 integer = 512'b0
G mem4 integer = 512'b0
G mem5 integer = 512'b0
G mem6 integer = 512'b0
G mem7 integer = 512'b0
G mem8 integer = 512'b0
G mem9 integer = 512'b0
G operation_mode string = "single_port"
G mixed_port_feed_through_mode string = "dont_care"
G ram_block_type string = "auto"
G logical_ram_name string = "ram_name"
G init_file string = "init_file.hex"
G init_file_layout string = "none"
G data_interleave_width_in_bits integer = 1
G data_interleave_offset_in_bits integer = 1
G port_a_logical_ram_depth integer = 0
G port_a_logical_ram_width integer = 0
G port_a_data_in_clear string = "none"
G port_a_address_clear string = "none"
G port_a_write_enable_clear string = "none"
G port_a_data_out_clock string = "none"
G port_a_data_out_clear string = "none"
G port_a_first_address integer = 0
G port_a_last_address integer = 0
G port_a_first_bit_number integer = 0
G port_a_byte_enable_clear string = "none"
G port_a_data_in_clock string = "clock0"
G port_a_address_clock string = "clock0"
G port_a_write_enable_clock string = "clock0"
G port_a_byte_enable_clock string = "clock0"
G port_b_logical_ram_depth integer = 0
G port_b_logical_ram_width integer = 0
G port_b_data_in_clock string = "none"
G port_b_data_in_clear string = "none"
G port_b_address_clock string = "none"
G port_b_address_clear string = "none"
G port_b_read_enable_write_enable_clock string = "none"
G port_b_read_enable_write_enable_clear string = "none"
G port_b_data_out_clock string = "none"
G port_b_data_out_clear string = "none"
G port_b_first_address integer = 0
G port_b_last_address integer = 0
G port_b_first_bit_number integer = 0
G port_a_data_width integer = 144
G port_b_data_width integer = 144
G port_a_address_width integer = 144
G port_b_address_width integer = 144
G port_b_byte_enable_clear string = "none"
G port_b_byte_enable_clock string = "none"
G port_a_byte_enable_mask_width integer = 144
G port_b_byte_enable_mask_width integer = 144
G lpm_type string = "stratix_ram_block"
G connectivity_checking string = "off"
P portadatain _in wire[143:0]
V portadatain - - - -
P portaaddr _in wire[15:0]
V portaaddr - - - -
P portawe _in wire
V portawe - - - -
P portbdatain _in wire[143:0]
V portbdatain - - - -
P portbaddr _in wire[15:0]
V portbaddr - - - -
P portbrewe _in wire
V portbrewe - - - -
P clk0 _in wire
V clk0 - - - -
P clk1 _in wire
V clk1 - - - -
P ena0 _in wire
V ena0 - - - -
P ena1 _in wire
V ena1 - - - -
P clr0 _in wire
V clr0 - - - -
P clr1 _in wire
V clr1 - - - -
P portabyteenamasks _in wire[15:0]
V portabyteenamasks - - - -
P portbbyteenamasks _in wire[15:0]
V portbbyteenamasks - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
P portadataout _out wire[143:0]
V portadataout - - - -
P portbdataout _out wire[143:0]
V portbdataout - - - -
X stratix_ram_block
V 000064 12 354 1071731857844 stratix_lvds_tx_parallel_register
E stratix_lvds_tx_parallel_register VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G channel_width integer = 4
P clk _in wire
V clk - - - -
P enable _in wire
V enable - - - -
P datain _in wire[9:0]
V datain - - - -
P dataout _out wire[9:0]
V dataout - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
X stratix_lvds_tx_parallel_register
V 000056 12 376 1071731857849 stratix_lvds_tx_out_block
E stratix_lvds_tx_out_block VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G bypass_serializer string = "false"
G invert_clock string = "false"
G use_falling_clock_edge string = "false"
P clk _in wire
V clk - - - -
P datain _in wire
V datain - - - -
P dataout _out wire
V dataout - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
X stratix_lvds_tx_out_block
V 000055 12 446 1071731857854 stratix_lvds_transmitter
E stratix_lvds_transmitter VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G channel_width integer = 4
G bypass_serializer string = "false"
G invert_clock string = "false"
G use_falling_clock_edge string = "false"
P clk0 _in wire
V clk0 - - - -
P enable0 _in wire
V enable0 - - - -
P datain _in wire[9:0]
V datain - - - -
P dataout _out wire
V dataout - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
X stratix_lvds_transmitter
V 000064 12 354 1071731857858 stratix_lvds_rx_parallel_register
E stratix_lvds_rx_parallel_register VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G channel_width integer = 4
P clk _in wire
V clk - - - -
P enable _in wire
V enable - - - -
P datain _in wire[9:0]
V datain - - - -
P dataout _out wire[9:0]
V dataout - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
X stratix_lvds_rx_parallel_register
V 000052 12 397 1071731857863 stratix_lvds_receiver
E stratix_lvds_receiver VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G channel_width integer = 4
G use_enable1 string = "false"
P clk0 _in wire
V clk0 - - - -
P enable0 _in wire
V enable0 - - - -
P enable1 _in wire
V enable1 - - - -
P datain _in wire
V datain - - - -
P dataout _out wire[9:0]
V dataout - - - -
P devclrn _in wire
V devclrn - - - -
P devpor _in wire
V devpor - - - -
X stratix_lvds_receiver
V 000037 12 294 1071731857867 m_cntr
E m_cntr VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P clk _in wire
V clk - - - -
P reset _in wire
V reset - - - -
P cout _out wire
V cout - - - -
P initial_value _in wire[31:0]
V initial_value - - - -
P modulus _in wire[31:0]
V modulus - - - -
P time_delay _in wire[31:0]
V time_delay - - - -
X m_cntr
V 000037 12 294 1071731857871 n_cntr
E n_cntr VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P clk _in wire
V clk - - - -
P reset _in wire
V reset - - - -
P cout _out wire
V cout - - - -
P initial_value _in wire[31:0]
V initial_value - - - -
P modulus _in wire[31:0]
V modulus - - - -
P time_delay _in wire[31:0]
V time_delay - - - -
X n_cntr
V 000041 12 409 1071731857875 scale_cntr
E scale_cntr VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P clk _in wire
V clk - - - -
P reset _in wire
V reset - - - -
P cout _out wire
V cout - - - -
P high _in wire[31:0]
V high - - - -
P low _in wire[31:0]
V low - - - -
P initial_value _in wire[31:0]
V initial_value - - - -
P mode _in wire[48:1]
V mode - - - -
P time_delay _in wire[31:0]
V time_delay - - - -
P ph_tap _in wire[31:0]
V ph_tap - - - -
X scale_cntr
V 000038 12 223 1071731857879 pll_reg
E pll_reg VERILOG 
L VL;
U VL.VERILOG_LOGIC;
P q _out reg
V q - - - -
P clk _in wire
V clk - - - -
P ena _in tri1
V ena - - - -
P d _in wire
V d - - - -
P clrn _in tri1
V clrn - - - -
P prn _in tri1
V prn - - - -
X pll_reg
V 000043 12 8779 1071731857883 stratix_pll
E stratix_pll VERILOG 
L VL;
U VL.VERILOG_LOGIC;
G operation_mode string = "normal"
G qualify_conf_done string = "off"
G compensate_clock string = "clk0"
G pll_type string = "auto"
G scan_chain string = "long"
G clk0_multiply_by integer = 1
G clk0_divide_by integer = 1
G clk0_phase_shift integer = 0
G clk0_time_delay integer = 0
G clk0_duty_cycle integer = 50
G clk1_multiply_by integer = 1
G clk1_divide_by integer = 1
G clk1_phase_shift integer = 0
G clk1_time_delay integer = 0
G clk1_duty_cycle integer = 50
G clk2_multiply_by integer = 1
G clk2_divide_by integer = 1
G clk2_phase_shift integer = 0
G clk2_time_delay integer = 0
G clk2_duty_cycle integer = 50
G clk3_multiply_by integer = 1
G clk3_divide_by integer = 1
G clk3_phase_shift integer = 0
G clk3_time_delay integer = 0
G clk3_duty_cycle integer = 50
G clk4_multiply_by integer = 1
G clk4_divide_by integer = 1
G clk4_phase_shift integer = 0
G clk4_time_delay integer = 0
G clk4_duty_cycle integer = 50
G clk5_multiply_by integer = 1
G clk5_divide_by integer = 1
G clk5_phase_shift integer = 0
G clk5_time_delay integer = 0
G clk5_duty_cycle integer = 50
G extclk0_multiply_by integer = 1
G extclk0_divide_by integer = 1
G extclk0_phase_shift integer = 0
G extclk0_time_delay integer = 0
G extclk0_duty_cycle integer = 50
G extclk1_multiply_by integer = 1
G extclk1_divide_by integer = 1
G extclk1_phase_shift integer = 0
G extclk1_time_delay integer = 0
G extclk1_duty_cycle integer = 50
G extclk2_multiply_by integer = 1
G extclk2_divide_by integer = 1
G extclk2_phase_shift integer = 0
G extclk2_time_delay integer = 0
G extclk2_duty_cycle integer = 50
G extclk3_multiply_by integer = 1
G extclk3_divide_by integer = 1
G extclk3_phase_shift integer = 0
G extclk3_time_delay integer = 0
G extclk3_duty_cycle integer = 50
G primary_clock string = "inclk0"
G inclk0_input_frequency integer = 10000
G inclk1_input_frequency integer = 10000
G gate_lock_signal string = "no"
G gate_lock_counter integer = 1
G valid_lock_multiplier integer = 5
G invalid_lock_multiplier integer = 5
G switch_over_on_lossclk string = "off"
G switch_over_on_gated_lock string = "off"
G switch_over_counter integer = 1
G enable_switch_over_counter string = "off"
G feedback_source string = "e0"
G bandwidth integer = 0
G bandwidth_type string = "auto"
G down_spread string = "0.0"
G spread_frequency integer = 0
G common_rx_tx string = "off"
G rx_outclock_resource string = "auto"
G use_vco_bypass string = "false"
G use_dc_coupling string = "false"
G pfd_min integer = 0
G pfd_max integer = 0
G vco_min integer = 0
G vco_max integer = 0
G vco_center integer = 0
G m_initial integer = 1
G m integer = 1
G n integer = 1
G m2 integer = 1
G n2 integer = 1
G ss integer = 0
G l0_high integer = 1
G l0_low integer = 1
G l0_initial integer = 1
G l0_mode string = "bypass"
G l0_ph integer = 0
G l0_time_delay integer = 0
G l1_high integer = 1
G l1_low integer = 1
G l1_initial integer = 1
G l1_mode string = "bypass"
G l1_ph integer = 0
G l1_time_delay integer = 0
G g0_high integer = 1
G g0_low integer = 1
G g0_initial integer = 1
G g0_mode string = "bypass"
G g0_ph integer = 0
G g0_time_delay integer = 0
G g1_high integer = 1
G g1_low integer = 1
G g1_initial integer = 1
G g1_mode string = "bypass"
G g1_ph integer = 0
G g1_time_delay integer = 0
G g2_high integer = 1
G g2_low integer = 1
G g2_initial integer = 1
G g2_mode string = "bypass"
G g2_ph integer = 0
G g2_time_delay integer = 0
G g3_high integer = 1
G g3_low integer = 1
G g3_initial integer = 1
G g3_mode string = "bypass"
G g3_ph integer = 0
G g3_time_delay integer = 0
G e0_high integer = 1
G e0_low integer = 1
G e0_initial integer = 1
G e0_mode string = "bypass"
G e0_ph integer = 0
G e0_time_delay integer = 0
G e1_high integer = 1
G e1_low integer = 1
G e1_initial integer = 1
G e1_mode string = "bypass"
G e1_ph integer = 0
G e1_time_delay integer = 0
G e2_high integer = 1
G e2_low integer = 1
G e2_initial integer = 1
G e2_mode string = "bypass"
G e2_ph integer = 0
G e2_time_delay integer = 0
G e3_high integer = 1
G e3_low integer = 1
G e3_initial integer = 1
G e3_mode string = "bypass"
G e3_ph integer = 0