rfcs_top.vhd

带有PPC405的Xilinx FPGA通过CPLD实现远程配置的设计

--	elsif rising_edge(clk25m) then											    			    
--		rstgen_bus(2 downto 0) <= rstgen_bus(1 downto 0) & gpio_reconfig1;
--	end if;																	  
--end process gpio_reconfig1_rst_gen;
--
--gpio_reconfig1_rst <= gpio_reconfig1 and (rstgen_bus(0) xor rstgen_bus(2));
--------------------------------------------------------------------------------------

----------------------------------------------------------------------------------------------
-- Generate reset when write_register(1) = '1' to clear S/W error status  
----------------------------------------------------------------------------------------------
--manual_reconfig_rst_gen : process(rst, clk25m,gpio_chk_en)
--begin
--	if rst = '0' then
--		rstgen_bus_a <= (others => '0');
--	elsif rising_edge(clk25m) then
--		if gpio_chk_en = '1' then 											    			    
--			rstgen_bus_a(2 downto 0) <= rstgen_bus_a(1 downto 0) & write_register(1);
--		end if;
--	end if;																	  
--end process manual_reconfig_rst_gen;

--manual_reconfig_rst <= write_register(1) and gpio_chk_en and (rstgen_bus_a(0) xor rstgen_bus_a(2));
 
------------------------------------------------------------------
-- Check if arrived at maximum address 
-- To prohibit infinity	loop when couldn't detect Sync. word
------------------------------------------------------------------
--  end_address <= '1' when (address = address_max) else '0';
--process (cclk, rst, address, load, gpio_reconfig_clk,manual_reconfig_rst)
--begin
--	if rst = '0' or gpio_reconfig_clk = '1' or manual_reconfig_rst = '1' then
--    	add_max_wd_cnt <= (others =>'0');
--		end_address <= '0';
--	elsif rising_edge(cclk) then
--		if add_max_wd_cnt = "111" then
--			end_address <= '1';
--		elsif (address = "11111111111111111111" and load = '1') then
--        	add_max_wd_cnt <= add_max_wd_cnt + '1'; 
--		end if;
--	end if;
--end process;

process (cclk, rst, fpga_init, load)
begin
	if rst = '0' or fpga_init = '0' then
    	add_max_wd_cnt <= (others =>'0');
		end_address <= '0';
	elsif rising_edge(cclk) then
		if add_max_wd_cnt = "111" then
			end_address <= '1';
	--	elsif (address = "11111111111111111111" and load = '1') then
		elsif (address(16 downto 0) = "11111111111111111" and load = '1') then
        	add_max_wd_cnt <= add_max_wd_cnt + '1'; 
		end if;
	end if;
end process;
----------------------------------------------------------------------------
--- Skip check CRC Error right after Power on & before start config. (INIT = '0' and Done = '0') 
-------------------------------------------------------------------------
process (fpga_init,rst)
begin
	if rst = '0' then
		chk_4try_en <= '0';
	elsif rising_edge(fpga_init) then
		chk_4try_en <= '1';
	end if;
end process;																	     
--
----------------------------------------------------------------------------------
------- Check CRC Error case                               -----------------------
-------  Init goes Low while Done is low (except Power on reset, INIT = '0' case)										  
----------------------------------------------------------------------------------
process (clk25m,rst,fpga_init,fpga_done,crc_wd_cnt,chk_4try_en)
begin
	if rst = '0' or fpga_init = '1' then
     	crc_wd_cnt <= (others =>'0');
		crc_error <= '0';
		crc_error_recfg <= '0';
	elsif rising_edge(clk25m) then
		if (fpga_init = '0' and fpga_done = '0' and chk_4try_en = '1') then --Ignor POR INIT 
			if crc_wd_cnt =   "1111111111111111" then	  --Real 			
	             -- if crc_wd_cnt = "0000000000011111"  then	--- For simulation 
				crc_error  <= '1';					 
				crc_wd_cnt <= "0000000000000000";
			elsif crc_wd_cnt(15 downto 4) = "111111111111" then    -- real 	
		     -- elsif crc_wd_cnt(15 downto 4) = "000000000001" then    --for Simulation 	
				crc_error_recfg <= '1';		    -- Drive Progb to low 16 clk25m period 
				crc_wd_cnt <= crc_wd_cnt + '1'; 
			else  
               			crc_wd_cnt <= crc_wd_cnt + '1'; 
				crc_error  <= '0'; 
				crc_error_recfg <= '0';
            		end if;
		end if;       
	end if;																	  
end process;
--
--------------CRC Error Check New ----------2004, Sep. 16 ---------
--- Sense Failling edge of INIT while Progb = '1' to distingush state from 
--- reconfig. state ------
--------------------------------------------------------------------------
--process (clk25m,rst)
--begin
--	if rst = '0' then
--		chk_failling_init_bus <= (others => '0');
--	elsif rising_edge(clk25m) then
----		if fpga_progb_in = '1' then 
--			chk_failling_init_bus(1 downto 0) <= chk_failling_init_bus(0) & fpga_init;
----		end if;
--        end if;															  
--end process;
--crc_error <= (not fpga_init)and fpga_progb_in and (chk_failling_init_bus(0) xor chk_failling_init_bus(1)); --failling edge 

----process (rst,fpga_progb_in,crc_error)
--process (rst,fpga_init,crc_error)
--begin
--	if rst = '0' or fpga_init = '1' then
--		crc_error_recfg <= '0';
--	elsif rising_edge(crc_error) then
--		crc_error_recfg <= '1';
 --      end if;															  
--end process;

-------------------------------------------------------------------------------------
----  Count Retry configuration 3 times on Update(User) area     --------------------
---- CRC Error case, FPGA regonfiguration is processing on upper CRC Error check routine
---- by driving crc_error_recfg <= '1';
-------------------------------------------------------------------------------------
process (clk25m, rst, crc_error, reconfig_clear)
begin  
--	if (rst = '0' or gpio_reconfig1 = '1' or manual_reconfig_rst = '1')then
	if (rst = '0' or reconfig_clear = '0')then
		cnt_retry <=(others => '0');
	elsif rising_edge(clk25m) then
		if (cnt_retry < "100") then
			if crc_error = '1' then
				cnt_retry <= cnt_retry + '1';
            end if;
		end if;
	end if;
end process;

------------------------------------------------------------------------------------
 no_sync_word <= (not fpga_done) and end_address;
------------------------------------------------------------------------------------
--- Check 3 times configuration try failure on Update area -------------------------
----    Then Change the bank to Factory default area -------------------------------
------------------------------------------------------------------------------------
--     Flash memory section
--     ----------------
--     |  User App     |
--     ---------------- <= 0x0460_0000
--     |  Fact App     |
--     ---------------- <= 0x0440_0000
--     |  User Bit     |
--     ----------------- <= 0x0420_0000 (flash address bus "01" & address), address20 = '1'
--     |  Fact Bit     |
--     ----------------- <= 0x0400_0000 (flash address bus "00" & address), adddres20 = '0'
--
------------------------------------------------------------------------------------
process(clk25m, fpga_done, rst, end_address,gpio_reconfig1)
begin  
	if rst = '0' then
     	address20 <= '1';	-- default user section
	elsif rising_edge(clk25m) then
		if (cnt_retry = "100" or no_sync_word = '1' or write_register(1) = '1' or software_fail = '1')  then
          		address20 <= '0'; -- if there is error, factory section
          	elsif gpio_reconfig1 = '1' then
          		address20 <= '1';
		end if;
	end if;
end process;


----------------------------------------------------------------------------------------------
-- If Software loaded successfully then it write '1' to write_register(0) but 
--    if write_register(0) not set to '1' within XXX Second then CPLD will retry FPGA configuration 
--     with Factory default configuration and get S/W fail status                        -----
----------------------------------------------------------------------------------------------
--process(clk25m)
--begin
--	if rising_edge(clk25m) then
--		sw_wd_cnt_en <= fpga_done;
--	end if;
--end process;		
--
reconfig_clear <= '0' when gpio_chk_en = '1' and (gpio_rdb = '0' and  gpio_reconfig = '0') else '1';

---- process (clk25m,fpga_init, write_register(0) )
--process(rst,clk25m,reconfig_clear)
--begin  
----	if(rst = '0' or manual_reconfig_rst = '1' or gpio_reconfig = '0') then
--        if(rst = '0' or reconfig_clear = '0') then
--     		sw_wd_cnta <= (others =>'0');
--	elsif rising_edge(clk25m) then
--		if write_register(0) = '0' and fpga_done = '1' then
--			sw_wd_cnta <= sw_wd_cnta + '1'; 
--			if sw_wd_cnta = "1111111111111" then  ---cnt X Clock Duration = S/W loading time 	-- if sw_wd_cnt = x"00000FF" then  ---For Simulation only 
--				sw_wd_cnta_tco <= '1';
--               		else 
--               			sw_wd_cnta_tco <= '0';
--               		end if;
--               	   
--		end if;
--	end if;
--end process;
--
--process(rst,clk25m,reconfig_clear)
--begin  
--	if(rst = '0' or reconfig_clear = '0') then
--     		sw_wd_cntb <= (others =>'0');
--		software_fail <= '0';
--	elsif rising_edge(clk25m) then
--		if (write_register(0) = '0' and fpga_done = '1') then
--			if sw_wd_cntb = "1111111111111" and sw_wd_cnta_tco = '1' then  ---cnt X Clock Duration = S/W loading time 	-- if sw_wd_cnt = x"00000FF" then  ---For Simulation only 
--				software_fail <= '1';
--			elsif sw_wd_cnta_tco = '1' then 				   
--               			sw_wd_cntb <= sw_wd_cntb + '1'; 
--               			software_fail <= '0';             
--			end if;
----		else 
----			software_fail <= '0';
--			-- sw_wd_cnt <= (others => '0');  
--		end if;
--	end if;
--end process;
----------------------Final ----------------
process(rst,clk25m,reconfig_clear,fpga_init)
begin  
	if(rst = '0' or reconfig_clear = '0' or fpga_init = '0') then
     		sw_wd_cntc <= (others =>'0');
		software_fail_detect <= '0';
	elsif rising_edge(clk25m) then
		if (write_register(0) = '0' and fpga_done = '1') then
			if sw_wd_cntc = "1111111111111111111111111111" then  ---cnt X Clock Duration = S/W loading time 	-- if sw_wd_cnt = x"00000FF" then  ---For Simulation only 
				software_fail_detect <= '1';
			else 				   
               			sw_wd_cntc <= sw_wd_cntc + '1'; 
               			software_fail_detect <= '0';             
			end if;

		end if;
	end if;
end process;
----------------------------------------------------------------------------------------------
-- set software fail latch
------------------------------------------------------------------------------------------------
process(rst,clk25m,reconfig_clear)
begin
	if (rst = '0' or reconfig_clear = '0') then 
		software_fail <= '0';
	elsif rising_edge(clk25m) then
		if software_fail_detect = '1' then
    		software_fail <= '1';
    	end if;
	end if;									    
end process;
--
----------------------------------------------------------------------------------------------
-- Three re-config. condition into one shift register to create PROG drive duration.      ----
-- When lost_fpga_config = '1' or end_address = '1' or (fwdone_reconfig_en and flash_wdone) = '1' 
-- Generate 16 cycle of high period 
--40ns(25 Mhz) * 16 = 640ns,     20ns(50Mhz) * 16 = 320ns	 : Max. freq. is 50Mhz for clk25m 
----------------------------------------------------------------------------------------------
reconfig_request <= software_fail or end_address or gpio_reconfig1 or write_register(1) or crc_error_recfg;

drive_prog : process(rst, clk25m, reconfig_request)
begin
	if rst = '0' then
		sft_bus <= (others => '0');
	elsif rising_edge(clk25m) then											    			    
		sft_bus(4 downto 0) <= sft_bus(3 downto 0) & reconfig_request;
	end if;																	  
end process drive_prog;

request_prog <= reconfig_request and (sft_bus(0) xor sft_bus(4));

------------------------------------------------------------------------------------------
--- Drive PROG pin to low to reconfigure FPGA 
------------------------------------------------------------------------------------------

--prog_tmp <= request_prog or crc_error_recfg; --2004.09.15 
prog_tmp <= request_prog;  ---2004, 09.16 

fpga_progb <= '0' when prog_tmp = '1' else 'Z'; --output path 
fpga_progb_in <= fpga_progb; --input path 

 LED6 <= fpga_progb_in;
 LED8 <= crc_error_recfg;
 TP1  <= crc_error;
end Behavioral;