📄 rfcs_top.vhd
字号:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rfcs_top is
Port (
clk25m : in std_logic; --25Mhz from Intel ETH PHY
-- rst : in std_logic;
--- Intel Flash Memory I/F
flash_dq : in std_logic_vector(15 downto 0);
flash_add : out std_logic_vector(21 downto 0);
flash_oeb : out std_logic;
flash_web : out std_logic;
flash_ceob : out std_logic;
flash_rpb : out std_logic;
-- flash_sts : out std_logic;
----- FPGA monitoring & configuration
cclk : in std_logic;
fpga_din : out std_logic;
fpga_init : in std_logic;
fpga_done : in std_logic;
fpga_progb : inout std_logic;
LED6 : out std_logic;
LED8 : out std_logic;
TP1 : out std_logic;
gpio_reconfig : in std_logic;
gpio_writeb : in std_logic;
gpio_rdb : in std_logic;
gpio_reg : inout std_logic_vector(2 downto 0)
);
end rfcs_top;
architecture Behavioral of rfcs_top is
signal cnt : std_logic_vector(3 downto 0);
signal gpio_chk_cnt : std_logic_vector(11 downto 0);
signal address : std_logic_vector(19 downto 0);
signal end_address,load : std_logic;
signal reconfig_request : std_logic;
signal latch_data,flash_dq_tmp : std_logic_vector(15 downto 0);
signal sft_bus : std_logic_vector(4 downto 0);
signal prog_tmp,request_prog : std_logic;
signal din_tmp : std_logic;
signal address20 : std_logic;
signal crc_wd_cnt : std_logic_vector(15 downto 0);
signal crc_error,crc_error_recfg : std_logic;
signal no_sync_word ,software_fail : std_logic;
signal chk_4try_en : std_logic;
signal cnt_retry,add_max_wd_cnt ,gpio_reconfig1_bus : std_logic_vector(2 downto 0);
signal gpio_reconfig1_rst,sw_fail_reg : std_logic;
signal rstgen_bus,write_register,rstgen_bus_a : std_logic_vector(2 downto 0);
-- signal sw_wd_cnta : std_logic_vector(12 downto 0);
-- signal sw_wd_cntb : std_logic_vector(12 downto 0);
signal sw_wd_cntc : std_logic_vector(27 downto 0);
-- signal sw_wd_cnta_tco : std_logic;
signal sw_wd_cnt_en : std_logic;
signal rst : std_logic;
signal rst_cnt : std_logic_vector(1 downto 0);
signal software_fail_detect : std_logic;
signal gpio_writeb1 : std_logic;
signal gpio_writeb2 : std_logic;
signal not_gpio_writeb1 : std_logic;
signal gpio_wr_en : std_logic;
signal gpio_reconfig1, gpio_reconfig2 : std_logic;
signal not_gpio_reconfig1 : std_logic;
signal gpio_reconfig_en : std_logic;
signal reconfig_by_gpio3 : std_logic;
signal manual_reconfig_rst : std_logic;
signal sft1_high, gpio_chk_en,reconfig_clear : std_logic;
signal fpga_progb_in,gpio_reconfig_clk : std_logic;
signal chk_failling_init_bus : std_logic_vector(1 downto 0);
begin
----------------------------------------------------------------
--Generate Power on Reset -------------------------
-- Optional part if have external Power on Reset input ---------
----------------------------------------------------------------
process(clk25m)
begin
if rising_edge(clk25m) then
if rst_cnt < "11" then
rst_cnt <= rst_cnt + '1';
rst <= '0';
elsif rst_cnt = "11" then
-- rst_cnt <= rst_cnt;
rst <= '1';
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- Intel Strata Flash Interface -------------------------------------------------
----------------------------------------------------------------------------------
flash_ceob <= '0' when fpga_done = '0' else 'Z';
flash_oeb <= '0' when fpga_done = '0' else 'Z';
flash_rpb <= '1' when fpga_done = '0' else 'Z';
flash_web <= '1' when fpga_done = '0' else 'Z';
flash_add <= '0' & address20 & address when fpga_done = '0' else (others => 'Z') ;
-----------------------------------------------------------------------------------
--Parallel to Serial Counter (count 0 to 15 ) --------------------------------
----------------------------------------------------------------------------------
process (cclk, fpga_done, fpga_init)
begin
if fpga_init = '0' then
cnt <= (others =>'0');
elsif rising_edge(cclk) then
if (fpga_done = '0') then
cnt <= cnt + '1';
else
cnt <= cnt;
end if;
end if;
end process;
------------------------------------------------------------------------------------
--- cycle the address counter after 16 data bits are transfered -----------
------------------------------------------------------------------------------------
process (cclk,fpga_init,cnt)
begin
if fpga_init = '0' then
address <= (others =>'0'); --- Real
-- address <= "11111111111111110000"; ---- for simulation
load <= '1';
elsif rising_edge(cclk) then
if(cnt(3) = '1' and cnt(2) = '0' and cnt(1) = '0' and cnt(0) = '1') then
address <= address + 1; --- Change Flash Address 6 CLOCK before load
elsif(cnt(3) = '1' and cnt(2) = '1' and cnt(1) = '1' and cnt(0) = '1') then
load <= '1'; --- To Load Flash Parallel data to Shift Register
else
address <= address;
load <= '0';
end if;
end if;
end process;
---------------------------------------------------------------------------------
--- When .Bit converted to .Bin or .Hex, Byte Swaping is required
---------------------------------------------------------------------------------
flash_dq_tmp(7 downto 0) <= flash_dq(15 downto 8);
flash_dq_tmp(15 downto 8) <= flash_dq(7 downto 0);
---------------------------------------------------------------------------------
---Latched Data shift and serial output to FPGA D0 to configure FPGA
---------------------------------------------------------------------------------
process(cclk, load,flash_dq_tmp,fpga_init)
variable latch_data : std_logic_vector(15 downto 0);
begin
if fpga_init = '0' then
din_tmp <= '1';
elsif rising_edge(cclk) then
-- elsif falling_edge(cclk) then
if (load = '1') then
latch_data(15 downto 0) := flash_dq_tmp(15 downto 0);
din_tmp <= flash_dq_tmp(0);
else
latch_data(15 downto 0) := 'Z' & latch_data(15 downto 1);
din_tmp <= latch_data(0);
end if;
end if;
end process;
fpga_din <= 'Z' when fpga_init = '0' else din_tmp;
-----------------------------------------------------------------------------------------
--Flash related status register
--use GPIO for readb, writeb and 3 data port
-- write_register(2) : S/W write this bit to '1' when request Reconfiguration (S/W should drive this reg. and gpio_reconfig)
-- User section to user section reconfiguration.
-- write_register(1) : Change the Flash bank to factory area and Reconfig. FPGA
-- '1' when request manual mode(drive request_factory) (S/W should drive this reg.)
-- write_register(0) : S/W set this register to '1' when S/W was loaded successfully (S/W should drive this reg.)
-- read_register(2) : Same as Write_register(2) , Reconfig. request was issued '1', or Normal '0'
-- read_register(1) : Same as Write_register(1) , Manual mode '1', or Normal mode '0'
-- read_register(0) : status for S/W fail , S/W fail '1', S/W OK '0'
process(clk25m,rst)
begin
if(rst = '0') then
gpio_writeb1 <= '1';
gpio_writeb2 <= '1';
elsif rising_edge(clk25m) then
gpio_writeb1 <= gpio_writeb;
gpio_writeb2 <= gpio_writeb1;
end if;
end process;
not_gpio_writeb1 <= not gpio_writeb1;
gpio_wr_en <= gpio_writeb2 and not_gpio_writeb1;
process(gpio_writeb,rst,clk25m)
begin
if(rst = '0') then
write_register <= (others => '0');
-- elsif falling_edge(gpio_writeb) then
elsif rising_edge(clk25m) then
if fpga_done = '1' and gpio_wr_en = '1' then
write_register <= gpio_reg;
end if;
end if;
end process;
gpio_reg <= write_register(2 downto 1) & software_fail when gpio_rdb = '0' else "ZZZ";
--
--process(clk25m,rst)
--begin
-- if(rst = '0') then
-- gpio_reconfig1 <= '1';
-- elsif rising_edge(clk25m) then
-- gpio_reconfig1 <= gpio_reconfig;
-- end if;
--end process;
--fw_done_recfg <= gpio_reconfig1;
--LED6 <= gpio_reconfig1;
--process(cclk,fpga_done)
--begin
-- if(fpga_done = '0') then
-- gpio_chk_en <= '0';
-- sft1_high <= '0';
-- elsif falling_edge(cclk) then
-- sft1_high <= '1';
-- gpio_chk_en <= sft1_high;
-- end if;
--end process;
--
process(clk25m, rst,fpga_init)
begin
if(rst = '0' or fpga_init = '0') then
gpio_chk_en <= '0';
gpio_chk_cnt <= (others => '0');
elsif rising_edge(clk25m) then
if fpga_done = '1' then
if gpio_chk_cnt = "111111111111" then
gpio_chk_en <= '1';
else
gpio_chk_cnt <= gpio_chk_cnt + '1';
gpio_chk_en <= '0';
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------------------------
-- Generate gpio_reconfig1
----------------------------------------------------------------------------------------------
gpio_reconfig1_gen : process(rst, clk25m, gpio_reconfig,gpio_chk_en,gpio_rdb,reconfig_clear)
begin
if rst = '0' or reconfig_clear = '0' then
gpio_reconfig1_bus <= (others => '0');
elsif rising_edge(clk25m) then
if gpio_chk_en = '1' and gpio_rdb = '1' then
gpio_reconfig1_bus(2 downto 0) <= gpio_reconfig1_bus(1 downto 0) & gpio_reconfig;
end if;
end if;
end process gpio_reconfig1_gen;
gpio_reconfig_clk <= (not gpio_reconfig)and gpio_rdb and gpio_chk_en and (gpio_reconfig1_bus(0) xor gpio_reconfig1_bus(2)); --failling edge
--gpio_reconfig1 <= (gpio_reconfig) and gpio_chk_en and (gpio_reconfig1_bus(0) xor gpio_reconfig1_bus(2)); --rising edge
process(gpio_reconfig_clk,rst,reconfig_clear,fpga_init)
begin
-- if rst = '0' or manual_reconfig_rst = '1' or gpio_reconfig = '0' then
if rst = '0' or reconfig_clear = '0' or fpga_init = '0' then
gpio_reconfig1 <= '0';
elsif rising_edge(gpio_reconfig_clk) then
if gpio_chk_en = '1' then
gpio_reconfig1 <= '1';
end if;
end if;
end process;
----------------------------------------------------------------------------------------------
-- Generate reset when gpio_reconfig1 = '1' or write_register(1) = '1' to restart 4 times try
------------------------------------------------------------------------------------------------
--gpio_reconfig1_rst_gen : process(rst, clk25m, gpio_reconfig1)
--begin
-- if rst = '0' then
-- rstgen_bus <= (others => '0');
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -