ft245_r_w.map.qmsg

USB芯片FT245BM读写代码,在Quartus II V7.2上测试成功!---Verilog语言.

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s7 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s7\" with stuck data_in port to stuck value GND" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s8 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s8\" with stuck data_in port to stuck value GND" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s9 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s9\" with stuck data_in port to stuck value GND" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s10 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s10\" with stuck data_in port to stuck value GND" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 16 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 2 " "Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "TX_state~60 " "Info: Register \"TX_state~60\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "RX_state~60 " "Info: Register \"RX_state~60\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Info: Found the following redundant logic cells in design" {  } {  } 0 0 "Found the following redundant logic cells in design" 0 0 "" 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/Study FPGA/FT245_R_W/FT245_R_W.map.smsg " "Info: Generated suppressed messages file E:/Study FPGA/FT245_R_W/FT245_R_W.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "878 " "Info: Implemented 878 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "17 " "Info: Implemented 17 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "819 " "Info: Implemented 819 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_RAMS" "21 " "Info: Implemented 21 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "182 " "Info: Allocated 182 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 23 00:10:23 2008 " "Info: Processing ended: Sat Feb 23 00:10:23 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Info: Elapsed time: 00:00:16" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}