ft245_r_w.tan.qmsg

USB芯片FT245BM读写代码,在Quartus II V7.2上测试成功!---Verilog语言.

{ "Info" "ITDB_TSU_RESULT" "data_to_usb\[0\] USB_TXE sclk 8.898 ns register " "Info: tsu for register \"data_to_usb\[0\]\" (data pin = \"USB_TXE\", clock pin = \"sclk\") is 8.898 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.815 ns + Longest pin register " "Info: + Longest pin to register delay is 11.815 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns USB_TXE 1 PIN PIN_13 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_13; Fanout = 8; PIN Node = 'USB_TXE'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { USB_TXE } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.009 ns) + CELL(0.292 ns) 8.770 ns data_to_usb\[0\]~313 2 COMB LC_X10_Y9_N8 8 " "Info: 2: + IC(7.009 ns) + CELL(0.292 ns) = 8.770 ns; Loc. = LC_X10_Y9_N8; Fanout = 8; COMB Node = 'data_to_usb\[0\]~313'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.301 ns" { USB_TXE data_to_usb[0]~313 } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.178 ns) + CELL(0.867 ns) 11.815 ns data_to_usb\[0\] 3 REG LC_X1_Y13_N8 1 " "Info: 3: + IC(2.178 ns) + CELL(0.867 ns) = 11.815 ns; Loc. = LC_X1_Y13_N8; Fanout = 1; REG Node = 'data_to_usb\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.045 ns" { data_to_usb[0]~313 data_to_usb[0] } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.628 ns ( 22.24 % ) " "Info: Total cell delay = 2.628 ns ( 22.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.187 ns ( 77.76 % ) " "Info: Total interconnect delay = 9.187 ns ( 77.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.815 ns" { USB_TXE data_to_usb[0]~313 data_to_usb[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.815 ns" { USB_TXE {} USB_TXE~out0 {} data_to_usb[0]~313 {} data_to_usb[0] {} } { 0.000ns 0.000ns 7.009ns 2.178ns } { 0.000ns 1.469ns 0.292ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 120 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"sclk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sclk 1 CLK PIN_153 387 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 387; CLK Node = 'sclk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns data_to_usb\[0\] 2 REG LC_X1_Y13_N8 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y13_N8; Fanout = 1; REG Node = 'data_to_usb\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { sclk data_to_usb[0] } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { sclk data_to_usb[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { sclk {} sclk~out0 {} data_to_usb[0] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.815 ns" { USB_TXE data_to_usb[0]~313 data_to_usb[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.815 ns" { USB_TXE {} USB_TXE~out0 {} data_to_usb[0]~313 {} data_to_usb[0] {} } { 0.000ns 0.000ns 7.009ns 2.178ns } { 0.000ns 1.469ns 0.292ns 0.867ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { sclk data_to_usb[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { sclk {} sclk~out0 {} data_to_usb[0] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "sclk USB_DATA\[4\] USB_WR~reg0 9.444 ns register " "Info: tco from clock \"sclk\" to destination pin \"USB_DATA\[4\]\" through register \"USB_WR~reg0\" is 9.444 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk source 2.925 ns + Longest register " "Info: + Longest clock path from clock \"sclk\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sclk 1 CLK PIN_153 387 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 387; CLK Node = 'sclk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns USB_WR~reg0 2 REG LC_X10_Y10_N8 15 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X10_Y10_N8; Fanout = 15; REG Node = 'USB_WR~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.456 ns" { sclk USB_WR~reg0 } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 120 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { sclk USB_WR~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { sclk {} sclk~out0 {} USB_WR~reg0 {} } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 120 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.295 ns + Longest register pin " "Info: + Longest register to pin delay is 6.295 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns USB_WR~reg0 1 REG LC_X10_Y10_N8 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y10_N8; Fanout = 15; REG Node = 'USB_WR~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { USB_WR~reg0 } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 120 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.221 ns) + CELL(2.074 ns) 6.295 ns USB_DATA\[4\] 2 PIN PIN_5 0 " "Info: 2: + IC(4.221 ns) + CELL(2.074 ns) = 6.295 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'USB_DATA\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.295 ns" { USB_WR~reg0 USB_DATA[4] } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.074 ns ( 32.95 % ) " "Info: Total cell delay = 2.074 ns ( 32.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.221 ns ( 67.05 % ) " "Info: Total interconnect delay = 4.221 ns ( 67.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.295 ns" { USB_WR~reg0 USB_DATA[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.295 ns" { USB_WR~reg0 {} USB_DATA[4] {} } { 0.000ns 4.221ns } { 0.000ns 2.074ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { sclk USB_WR~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { sclk {} sclk~out0 {} USB_WR~reg0 {} } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.295 ns" { USB_WR~reg0 USB_DATA[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.295 ns" { USB_WR~reg0 {} USB_DATA[4] {} } { 0.000ns 4.221ns } { 0.000ns 2.074ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}