prev_cmp_ft245_r_w.tan.qmsg

USB芯片FT245BM读写代码,在Quartus II V7.2上测试成功!---Verilog语言.

{ "Info" "ITDB_TSU_RESULT" "data_to_usb\[5\] WR_Enable sclk 8.821 ns register " "Info: tsu for register \"data_to_usb\[5\]\" (data pin = \"WR_Enable\", clock pin = \"sclk\") is 8.821 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.738 ns + Longest pin register " "Info: + Longest pin to register delay is 11.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns WR_Enable 1 PIN PIN_227 12 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_227; Fanout = 12; PIN Node = 'WR_Enable'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { WR_Enable } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.734 ns) + CELL(0.442 ns) 8.651 ns data_to_usb\[0\]~313 2 COMB LC_X12_Y12_N1 8 " "Info: 2: + IC(6.734 ns) + CELL(0.442 ns) = 8.651 ns; Loc. = LC_X12_Y12_N1; Fanout = 8; COMB Node = 'data_to_usb\[0\]~313'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.176 ns" { WR_Enable data_to_usb[0]~313 } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.220 ns) + CELL(0.867 ns) 11.738 ns data_to_usb\[5\] 3 REG LC_X3_Y15_N5 1 " "Info: 3: + IC(2.220 ns) + CELL(0.867 ns) = 11.738 ns; Loc. = LC_X3_Y15_N5; Fanout = 1; REG Node = 'data_to_usb\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.087 ns" { data_to_usb[0]~313 data_to_usb[5] } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.784 ns ( 23.72 % ) " "Info: Total cell delay = 2.784 ns ( 23.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.954 ns ( 76.28 % ) " "Info: Total interconnect delay = 8.954 ns ( 76.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.738 ns" { WR_Enable data_to_usb[0]~313 data_to_usb[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.738 ns" { WR_Enable {} WR_Enable~out0 {} data_to_usb[0]~313 {} data_to_usb[5] {} } { 0.000ns 0.000ns 6.734ns 2.220ns } { 0.000ns 1.475ns 0.442ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 120 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"sclk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sclk 1 CLK PIN_153 386 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 386; CLK Node = 'sclk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns data_to_usb\[5\] 2 REG LC_X3_Y15_N5 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X3_Y15_N5; Fanout = 1; REG Node = 'data_to_usb\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { sclk data_to_usb[5] } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 120 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { sclk data_to_usb[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { sclk {} sclk~out0 {} data_to_usb[5] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.738 ns" { WR_Enable data_to_usb[0]~313 data_to_usb[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.738 ns" { WR_Enable {} WR_Enable~out0 {} data_to_usb[0]~313 {} data_to_usb[5] {} } { 0.000ns 0.000ns 6.734ns 2.220ns } { 0.000ns 1.475ns 0.442ns 0.867ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { sclk data_to_usb[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { sclk {} sclk~out0 {} data_to_usb[5] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "sclk USB_DATA\[4\] USB_WR~reg0 9.042 ns register " "Info: tco from clock \"sclk\" to destination pin \"USB_DATA\[4\]\" through register \"USB_WR~reg0\" is 9.042 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sclk source 2.925 ns + Longest register " "Info: + Longest clock path from clock \"sclk\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sclk 1 CLK PIN_153 386 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 386; CLK Node = 'sclk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sclk } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns USB_WR~reg0 2 REG LC_X12_Y11_N8 15 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X12_Y11_N8; Fanout = 15; REG Node = 'USB_WR~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.456 ns" { sclk USB_WR~reg0 } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 120 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { sclk USB_WR~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { sclk {} sclk~out0 {} USB_WR~reg0 {} } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 120 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.893 ns + Longest register pin " "Info: + Longest register to pin delay is 5.893 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns USB_WR~reg0 1 REG LC_X12_Y11_N8 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y11_N8; Fanout = 15; REG Node = 'USB_WR~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { USB_WR~reg0 } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 120 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.819 ns) + CELL(2.074 ns) 5.893 ns USB_DATA\[4\] 2 PIN PIN_5 0 " "Info: 2: + IC(3.819 ns) + CELL(2.074 ns) = 5.893 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'USB_DATA\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.893 ns" { USB_WR~reg0 USB_DATA[4] } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.074 ns ( 35.19 % ) " "Info: Total cell delay = 2.074 ns ( 35.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.819 ns ( 64.81 % ) " "Info: Total interconnect delay = 3.819 ns ( 64.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.893 ns" { USB_WR~reg0 USB_DATA[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.893 ns" { USB_WR~reg0 {} USB_DATA[4] {} } { 0.000ns 3.819ns } { 0.000ns 2.074ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.925 ns" { sclk USB_WR~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.925 ns" { sclk {} sclk~out0 {} USB_WR~reg0 {} } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.893 ns" { USB_WR~reg0 USB_DATA[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.893 ns" { USB_WR~reg0 {} USB_DATA[4] {} } { 0.000ns 3.819ns } { 0.000ns 2.074ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "USB_RXF altera_auto_signaltap_0_USB_RXF_ae 10.624 ns Longest " "Info: Longest tpd from source pin \"USB_RXF\" to destination pin \"altera_auto_signaltap_0_USB_RXF_ae\" is 10.624 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns USB_RXF 1 PIN PIN_14 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_14; Fanout = 8; PIN Node = 'USB_RXF'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { USB_RXF } "NODE_NAME" } } { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.670 ns) + CELL(0.292 ns) 9.431 ns altera_auto_signaltap_0_USB_RXF_signaltap_lcell 2 COMB LC_X22_Y12_N6 1 " "Info: 2: + IC(7.670 ns) + CELL(0.292 ns) = 9.431 ns; Loc. = LC_X22_Y12_N6; Fanout = 1; COMB Node = 'altera_auto_signaltap_0_USB_RXF_signaltap_lcell'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.962 ns" { USB_RXF altera_auto_signaltap_0_USB_RXF_signaltap_lcell } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.193 ns) + CELL(0.000 ns) 10.624 ns altera_auto_signaltap_0_USB_RXF_ae 3 PIN LC_X22_Y13_N0 0 " "Info: 3: + IC(1.193 ns) + CELL(0.000 ns) = 10.624 ns; Loc. = LC_X22_Y13_N0; Fanout = 0; PIN Node = 'altera_auto_signaltap_0_USB_RXF_ae'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.193 ns" { altera_auto_signaltap_0_USB_RXF_signaltap_lcell altera_auto_signaltap_0_USB_RXF_ae } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.761 ns ( 16.58 % ) " "Info: Total cell delay = 1.761 ns ( 16.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.863 ns ( 83.42 % ) " "Info: Total interconnect delay = 8.863 ns ( 83.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.624 ns" { USB_RXF altera_auto_signaltap_0_USB_RXF_signaltap_lcell altera_auto_signaltap_0_USB_RXF_ae } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.624 ns" { USB_RXF {} USB_RXF~out0 {} altera_auto_signaltap_0_USB_RXF_signaltap_lcell {} altera_auto_signaltap_0_USB_RXF_ae {} } { 0.000ns 0.000ns 7.670ns 1.193ns } { 0.000ns 1.469ns 0.292ns 0.000ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}