prev_cmp_ft245_r_w.map.qmsg

USB芯片FT245BM读写代码,在Quartus II V7.2上测试成功!---Verilog语言.

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/altdpram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/altdpram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altdpram " "Info: Found entity 1: altdpram" {  } { { "altdpram.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altdpram.tdf" 180 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "lpm_mux.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_mux.tdf" 74 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_sgc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_sgc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_sgc " "Info: Found entity 1: mux_sgc" {  } { { "db/mux_sgc.tdf" "" { Text "E:/Study FPGA/FT245_R_W/db/mux_sgc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "lpm_decode.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_decode.tdf" 64 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_9jf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_9jf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_9jf " "Info: Found entity 1: decode_9jf" {  } { { "db/decode_9jf.tdf" "" { Text "E:/Study FPGA/FT245_R_W/db/decode_9jf.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/LPM_COUNTER.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/LPM_COUNTER.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "LPM_COUNTER.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/LPM_COUNTER.tdf" 248 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_m3i.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_m3i.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_m3i " "Info: Found entity 1: cntr_m3i" {  } { { "db/cntr_m3i.tdf" "" { Text "E:/Study FPGA/FT245_R_W/db/cntr_m3i.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_rpi.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_rpi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_rpi " "Info: Found entity 1: cntr_rpi" {  } { { "db/cntr_rpi.tdf" "" { Text "E:/Study FPGA/FT245_R_W/db/cntr_rpi.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_t3i.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_t3i.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_t3i " "Info: Found entity 1: cntr_t3i" {  } { { "db/cntr_t3i.tdf" "" { Text "E:/Study FPGA/FT245_R_W/db/cntr_t3i.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_cmi.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_cmi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_cmi " "Info: Found entity 1: cntr_cmi" {  } { { "db/cntr_cmi.tdf" "" { Text "E:/Study FPGA/FT245_R_W/db/cntr_cmi.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_AE_SUCCESSFUL" "auto_signaltap_0 " "Info: Analysis and Synthesis generated SignalTap II or debug node instance \"auto_signaltap_0\"" {  } {  } 0 0 "Analysis and Synthesis generated SignalTap II or debug node instance \"%1!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|FT245_R_W\|TX_state 2 " "Info: State machine \"\|FT245_R_W\|TX_state\" contains 2 states" {  } { { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 41 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|FT245_R_W\|RX_state 2 " "Info: State machine \"\|FT245_R_W\|RX_state\" contains 2 states" {  } { { "MyDD/FT245_R_W.v" "" { Text "E:/Study FPGA/FT245_R_W/MyDD/FT245_R_W.v" 40 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}