manchesterdeencoder.tan.summary

来自「基于FPGA/CPLD」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.299 ns
From           : din
To             : data_rise
From Clock     : 
To Clock       : clkx16
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 4.914 ns
From           : clkx2_r
To             : clkx2
From Clock     : clkx16
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.980 ns
From           : din
To             : data_temp
From Clock     : 
To Clock       : clkx16
Failed Paths   : 0

Type           : Clock Setup: 'clkx16'
Slack          : N/A
Required Time  : None
Actual Time    : 240.27 MHz ( period = 4.162 ns )
From           : add
To             : cnt[1]
From Clock     : clkx16
To Clock       : clkx16
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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