rcvr_tf.v.bak

一个通用串口的verilog源程序

`timescale 1 ns / 1 ns

// TOOL:     Project Navigator 
// DATE:     Fri Apr 14 17:32:41 2000 
// TITLE:    
// MODULE:   rcvr
// DESIGN:   rcvr
// FILENAME: rcvr
// PROJECT:  receive
// VERSION:  Version
// NOTE: DO NOT EDIT THIS FILE
// This file is auto generated by the Xilinx Design System

module testbench ;

// Inputs
    reg rxd;
    reg clk16x;
    reg rst;
    reg rdn;


// Outputs
    wire [7:0] dout;
    wire data_ready;
    wire framing_error;
    wire parity_error;


// Bidirs


// Instantiate the UUT
    rcvr d (
        .rxd(rxd), 
        .clk16x(clk16x), 
        .rst(rst), 
        .rdn(rdn), 
        .dout(dout), 
        .data_ready(data_ready), 
        .framing_error(framing_error), 
        .parity_error(parity_error)
        );


// Initialize Inputs
//    `ifdef auto_init

        initial begin
            rxd = 1;
            clk16x = 0;
            rst = 0;
            rdn = 1;
        end

//   `endif

always #10 clk16x = ~clk16x ;

initial begin
#1 rst = 1'b1 ;
#21 rst = 1'b0 ;
#350 rxd = 1'b0 ;
#1800 rxd = 1'b1 ;
#1800 rxd = 1'b0 ;
#1000 rdn = 1'b0 ;
#500 rdn = 1'b1 ;
end

endmodule