txmit_tf.v

一个通用串口的verilog源程序

`timescale 1 ns / 1 ns

// TOOL:     Project Navigator 
// DATE:     Fri Apr 14 14:26:16 2000 
// TITLE:    
// MODULE:   txmit
// DESIGN:   txmit
// FILENAME: txmit
// PROJECT:  transmit
// VERSION:  Version
// NOTE: DO NOT EDIT THIS FILE
// This file is auto generated by the Xilinx Design System

// Run sim 10 usec and see 11110000 and 10101010 patterns on sdo

module testbench_TX;

// Inputs
    reg [7:0] din;
    reg rst;
    reg clk16x;
    reg wrn;


// Outputs
    wire tbre;
    wire tsre;
    wire sdo;


// Bidirs


// Instantiate the UUT
    txmit d (
        .tbre(tbre), 
        .tsre(tsre), 
        .sdo(sdo), 
        .din(din), 
        .rst(rst), 
        .clk16x(clk16x), 
        .wrn(wrn)
        );


// Initialize Inputs
//    `ifdef auto_init

        initial begin
            din = 0;
            rst = 0;
            clk16x = 0;
            wrn = 1;
        end

//    `endif

always #10 clk16x = ~clk16x ;

initial begin
#3 rst = 1'b1 ;
din = 8'b11110000 ;
#25 rst = 1'b0 ;
#30 wrn = 1'b0 ;
#150 wrn = 1'b1 ;
#4000 din = 8'b10101010 ;
#870 wrn = 1'b0 ;
#200 wrn = 1'b1 ;
#3000 rst = 1'b1 ;
end

endmodule